Jonathan A. Clarke

Orcid: 0000-0003-1495-7746

According to our database1, Jonathan A. Clarke authored at least 8 papers between 2005 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Word-length selection for power minimization via nonlinear optimization.
ACM Trans. Design Autom. Electr. Syst., 2009

2008
Glitch-aware output switching activity from word-level statistics.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
On the feasibility of early routing capacitance estimation for FPGAs.
Proceedings of the FPL 2007, 2007

2006
Fast word-level power models for synthesis of FPGA-based arithmetic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Modeling of glitch effects in FPGA based arithmetic circuits.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

PowerBit - power aware arithmetic bit-width optimization.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Parameterized Logic Power Consumption Models for FPGA based Systems.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005


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