Peter Y. K. Cheung

According to our database1, Peter Y. K. Cheung authored at least 266 papers between 1991 and 2020.

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Bibliography

2020
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference.
IEEE Trans. Computers, 2020

2019
Context-based image acquisition from memory in digital systems.
J. Real Time Image Process., 2019

Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going.
ACM Comput. Surv., 2019

Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

LUTNet: Rethinking Inference in FPGA Soft Logic.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs.
ACM Trans. Reconfigurable Technol. Syst., 2018

CypherDB: A Novel Architecture for Outsourcing Secure Database Processing.
IEEE Trans. Cloud Comput., 2018

KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications.
Proceedings of the International Workshop on OpenCL, 2018

Accelerating Top-k ListNet Training for Ranking Using FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

A PYNQ-Based Framework for Rapid CNN Prototyping.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Hardware Compilation of Deep Neural Networks: An Overview.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications.
IEEE Des. Test, 2017

STRIPE: Signal selection for runtime power estimation.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms.
SIGARCH Comput. Archit. News, 2016

Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems.
ACM Trans. Reconfigurable Technol. Syst., 2015

G-DMA: improving memory access performance for hardware accelerated sparse graph computation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Preface.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Mitigation of process variation effect in FPGAs with partial rerouting method.
IEICE Electron. Express, 2014

Classification on variation maps: a new placement strategy to alleviate process variation on FPGA.
IEICE Electron. Express, 2014

Kernel-based Adaptive Image Sampling.
Proceedings of the VISAPP 2014, 2014

Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Dynamic voltage & frequency scaling with online slack measurement.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Timing Fault Detection in FPGA-Based Circuits.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Image progressive acquisition for hardware systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Accelerating sequential Monte Carlo method for real-time air traffic management.
SIGARCH Comput. Archit. News, 2013

High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration.
J. Syst. Archit., 2013

Variation and Reliability in FPGAs.
IEEE Des. Test, 2013

Domain-specific progressive sampling of face images.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Datapath fault tolerance for parallel accelerators.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Acceleration of real-time Proximity Query for dynamic active constraints.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

SMI: Slack Measurement Insertion for online timing monitoring in FPGAs.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A variation-adaptive retiming method exploiting reconfigurability.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Roberts: reconfigurable platform for benchmarking real-time systems.
SIGARCH Comput. Archit. News, 2012

Early performance estimation of image compression methods on soft processors.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A two-stage variation-aware placement method for FPGAS exploiting variation maps classification.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Adaptive Sequential Monte Carlo approach for real-time applications.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Introduction to special section FPGA 2009.
ACM Trans. Reconfigurable Technol. Syst., 2011

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network.
IEEE Trans. Ind. Electron., 2011

A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors.
Trans. High Perform. Embed. Archit. Compil., 2011

Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array.
IET Comput. Digit. Tech., 2011

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization.
Comput. J., 2011

Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Improving FPGA Reliability with Wear-Levelling.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Improved delay measurement method in FPGA based on transition probability.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2010

An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays.
ACM Trans. Reconfigurable Technol. Syst., 2010

Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods.
ACM Trans. Reconfigurable Technol. Syst., 2010

Benchmarking and evaluating reconfigurable architectures targeting the mobile domain.
ACM Trans. Design Autom. Electr. Syst., 2010

FPGA Architecture Optimization Using Geometric Programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study.
IEEE Trans. Computers, 2010

Wave-pipelined intra-chip signaling for on-FPGA communications.
Integr., 2010

Power Characterisation for Fine-Grain Reconfigurable Fabrics.
Int. J. Reconfigurable Comput., 2010

Fault tolerance and reliability in field-programmable gate arrays.
IET Comput. Digit. Tech., 2010

A Salient Region Detector for GPU Using a Cellular Automata Architecture.
Proceedings of the Neural Information Processing. Models and Applications, 2010

Degradation Analysis and Mitigation in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

GPU Versus FPGA for High Productivity Computing.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Degradation in FPGAs: measurement and modelling.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Energy-Aware Optimisation for Run-Time Reconfiguration.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Exploration of hardware sharing for image encoders.
Proceedings of the Design, Automation and Test in Europe, 2010

Process Variability and Degradation: New Frontier for Reconfigurable.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Self-Measurement of Combinatorial Circuit Delays in FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2009

Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2009

Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement.
ACM Trans. Reconfigurable Technol. Syst., 2009

Word-length selection for power minimization via nonlinear optimization.
ACM Trans. Design Autom. Electr. Syst., 2009

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems.
IET Comput. Digit. Tech., 2009

Hardware architectures for eigenvalue computation of real symmetric matrices.
IET Comput. Digit. Tech., 2009

High-throughput one-dimensional median and weighted median filters on FPGA.
IET Comput. Digit. Tech., 2009

Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A sensor-based approach to linear blur identification for real-time video enhancement.
Proceedings of the International Conference on Image Processing, 2009

Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Area estimation and optimisation of FPGA routing fabrics.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Compensating for variability in FPGAs by re-mapping and re-placement.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Benchmarking Reconfigurable Architectures in the Mobile Domain.
Proceedings of the FCCM 2009, 2009

Partition-based exploration for reconfigurable JPEG designs.
Proceedings of the Design, Automation and Test in Europe, 2009

A DP-network for optimal dynamic routing in network-on-chip.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep.
Proceedings of the Reconfigurable Computing: Architectures, 2009

Parametric Design for Reconfigurable Software-Defined Radio.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs.
J. Signal Process. Syst., 2008

Outer Loop Pipelining for Application Specific Datapaths in FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations.
ACM Trans. Reconfigurable Technol. Syst., 2008

Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information.
IEEE Trans. Multim., 2008

Custom parallel caching schemes for hardware-accelerated image compression.
J. Real Time Image Process., 2008

Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber.
Comput. J., 2008

Interconnection lengths and delays estimation for communication links in FPGAs.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Global interconnections in FPGAs: modeling and performance analysis.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Systematic design space exploration for customisable multi-processor architectures.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Implementation of Wave-Pipelined Interconnects in FPGAs.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Characterisation of FPGA Clock Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Glitch-aware output switching activity from word-level statistics.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Video enhancement on an adaptive image sensor.
Proceedings of the International Conference on Image Processing, 2008

A transition probability based delay measurement method for arbitrary circuits on FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Co-optimisation of datapath and memory in outer loop pipelining.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Modelling and compensating for clock skew variability in FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Wave-pipelined signaling for on-FPGA communication.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Combating process variation on FPGAS with a precise at-speed delay measurement method.
Proceedings of the FPL 2008, 2008

Fault tolerant methods for reliability in FPGAs.
Proceedings of the FPL 2008, 2008

Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework.
Proceedings of the FPL 2008, 2008

Towards benchmarking energy efficiency of reconfigurable architectures.
Proceedings of the FPL 2008, 2008

Measuring and modeling FPGA clock variability.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

High-throughput interconnect wave-pipelining for global communication in FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Using Reconfigurable Logic to Optimise GPU Memory Accesses.
Proceedings of the Design, Automation and Test in Europe, 2008

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation.
Proceedings of the Visions of Computer Science, 2008

FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Run-Time Integration of Reconfigurable Video Processing Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Real-time hardware acceleration of the trace transform.
J. Real Time Image Process., 2007

ROM to DSP block transfer for resource constrained synthesis.
IET Comput. Digit. Tech., 2007

A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory".
Proceedings of the First IEEE International Conference on Semantic Computing (ICSC 2007), 2007

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information.
Proceedings of the 15th International Conference on Multimedia 2007, 2007

A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information.
Proceedings of the International Conference on Image Processing, 2007

Self-characterization of Combinatorial Circuit Delays in FPGAs.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion.
Proceedings of the FPL 2007, 2007

On the feasibility of early routing capacitance estimation for FPGAs.
Proceedings of the FPL 2007, 2007

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Automatic On-chip Memory Minimization for Data Reuse.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

A Hybrid Memory Sub-system for Video Coding Applications.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

On-Chip Communication in Run-Time Assembled Reconfigurable Systems.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Fast word-level power models for synthesis of FPGA-based arithmetic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Spatiotemporal Saliency Framework.
Proceedings of the International Conference on Image Processing, 2006

User Attention Based Arousal Content Modeling.
Proceedings of the International Conference on Image Processing, 2006

Within-die delay variability in 90nm FPGAs and beyond.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A statistical framework for dimensionality reduction implementation in FPGAs.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A comparison of 2-D discrete wavelet transform computation schedules on FPGAs.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

The cost of data dependence in motion vector estimation for reconfigurable platforms.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

On-FPGA Communication Architectures and Design Factors.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Efficient Realtime FPGA Implementation of the Trace Transform.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Yield enhancements of design-specific FPGAs.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Hardware efficient architectures for Eigenvalue computation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

A Flexible Multi-port Caching Scheme for Reconfigurable Platforms.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Optimum and heuristic synthesis of multiple word-length architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Customizable elliptic curve cryptosystems.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A heuristic approach for multiple restricted multiplication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel 2D filter design methodology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

FPGA Based Router for Cognitive Packet Networks.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Have GPUs Made FPGAs Redundant in the Field of Video Processing?
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

An Analytical Approach to Generation and Exploration of Reconfigurable Architectures.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Power and Area Optimization for Multiple Restricted Multiplication.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Heterogeneity Exploration for Multiple 2D Filter Designs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Exploration of heterogeneous reconfigurable architectures (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

A Novel 2D Filter Design Methodology for Heterogeneous Devices.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Cell Based Motion Estimators for Reconfigurable Platforms.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Hardware Acceleration of Hidden Markov Model Decoding for Person Detection.
Proceedings of the 2005 Design, 2005

Reconfigurable Elliptic Curve Cryptosystems on a Chip.
Proceedings of the 2005 Design, 2005

Automating custom-precision function evaluation for embedded processors.
Proceedings of the 2005 International Conference on Compilers, 2005

2004
A Gaussian Noise Generator for Hardware-Based Simulations.
IEEE Trans. Computers, 2004

Guest Editors' Introduction: Field Programmable Logic and Applications.
IEEE Trans. Computers, 2004

Autonomous Memory Block for reconfigurable computing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Scalable structured data access by combining autonomous memory blocks.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

A scalable hardware architecture for prime number validation.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Multiple Restricted Multiplication.
Proceedings of the Field Programmable Logic and Application, 2004

A Structured Methodology for System-on-an-FPGA Design.
Proceedings of the Field Programmable Logic and Application, 2004

SoftSONIC: A Customisable Modular Platform for Video Applications.
Proceedings of the Field Programmable Logic and Application, 2004

Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation.
Proceedings of the Field Programmable Logic and Application, 2004

BIST Based Interconnect Fault Location for FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004

A Steerable Complex Wavelet Construction and Its Implementation on FPGA.
Proceedings of the Field Programmable Logic and Application, 2004

A Structured System Methodology for FPGA Based System-on-A-Chip Design.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Migrating Functionality from ROMS to Embedded Multipliers.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

A Novel Implementation of Tile-Based Address Mapping.
Proceedings of the 2004 Design, 2004

Synthesis and optimization of DSP algorithms.
Kluwer, ISBN: 978-1-4020-7930-6, 2004

2003
Synthesis of saturation arithmetic architectures.
ACM Trans. Design Autom. Electr. Syst., 2003

Wordlength optimization for linear digital signal processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

SONICmole: a debugging environment for the UltraSONIC reconfigurable computer.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Multitasking in hardware-software codesign for reconfigurable computer.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Architectures for function evaluation on FPGAs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Hierarchical segmentation schemes for function evaluation.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

High-level language extensions for run-time reconfigurable systems.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Reconfigurable Platform for Real-Time Embedded Video Image Processing.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Globally Asynchronous Locally Synchronous FPGA Architectures.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Non-uniform Segmentation for Hardware Function Evaluation.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Hardware Gaussian Noise Generator for Channel Code Evaluation.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Mesh Partitioning Approach to Energy Efficient Data Layout.
Proceedings of the 2003 Design, 2003

2002
Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign.
Des. Autom. Embed. Syst., 2002

Energy efficient address assignment through minimized memory row switching.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

PD-XML: extensible markup language for processor description.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Incremental programming for reconfigurable engines.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Strassen's matrix multiplication for customisable processors.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Floating-point bitwidth analysis via automatic differentiation.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Run-Time Adaptive Flexible Instruction Processors.
Proceedings of the Field-Programmable Logic and Applications, 2002

Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer.
Proceedings of the Field-Programmable Logic and Applications, 2002

Automating Customisation of Floating-Point Designs.
Proceedings of the Field-Programmable Logic and Applications, 2002

Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Reconfigurable Shape-Adaptive Template Matching Architectures.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Customising Floating-Point Designs.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Optimum Wordlength Allocation.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory.
Proceedings of the 2002 Design, 2002

2001
Quantitative Analysis of FPGA-based Database Searching.
J. VLSI Signal Process., 2001

MASH delta-sigma modulators for wideband and multi-standard applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A Digit-Serial Structure for Reconfigurable Multipliers.
Proceedings of the Field-Programmable Logic and Applications, 2001

The Effect of FPGA Granularity on Video Codec Implementations.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

The Multiple Wordlength Paradigm.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Heuristic datapath allocation for multiple wordlength systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Video Image Processing with the Sonic Architecture.
Computer, 2000

Roundoff-noise shaping in filter design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT.
Proceedings of the Field-Programmable Logic and Applications, 2000

Multiple-Wordlength Resource Binding.
Proceedings of the Field-Programmable Logic and Applications, 2000

Multiple Precision for Resource Minimization.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Flexible instruction processors.
Proceedings of the 2000 International Conference on Compilers, 2000

1999
Quantitative Analysis of Run-Time Reconfigurable Database Search.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

SONIC - A Plug-In Architecture for Video Processing.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

<i>Synthia</i>: Synthesis of Interacting Automata Targeting LUT-based FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Reconfigurable Computing for Augmented Reality.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
Run-Time Management of Dynamically Recongigurable Designs.
Proceedings of the Field-Programmable Logic and Applications, 1998

Automating Production of Run-Time Reconfigurable Designs.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
Modelling and Handling Uncertainties in Mobile Robotics.
J. Intell. Fuzzy Syst., 1997

Diagnosis of Boards for Realistic Interconnect Shorts.
J. Electron. Test., 1997

Asnchronous Wrapper for Heterogeneous Systems.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Pipeline morphing and virtual pipelines.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

A reconfigurable data-localised array for morphological algorithms.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Compilation tools for run-time reconfigurable designs.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

Improved diagnosis of realistic interconnect shorts.
Proceedings of the European Design and Test Conference, 1997

A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1996
Hierarchical tolerance analysis using statistical behavioral models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Adaptive Automatic Facial Feature Segmentation.
Proceedings of the 2nd International Conference on Automatic Face and Gesture Recognition (FG '96), 1996

Modelling and optimising run-time reconfigurable systems.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

On the viability of FPGA-based integrated coprocessors.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

Realistic Fault Extraction for Boards.
Proceedings of the 1996 European Design and Test Conference, 1996

An incremental machine learning mechanism applied to robot navigation.
Proceedings of the Australian New Zealand Conference on Intelligent Information Systems, 1996

Combining goal-directed, reactive and reflexive navigation in autonomous mobile robots.
Proceedings of the Australian New Zealand Conference on Intelligent Information Systems, 1996

1994
A Method of Representative Fault Selection in Digital Circuits for ATPG.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Virtual Hardware and the Limits of Computational Speed-up.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Analog Fault Diagnosis - A Practical Approach.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Area & Time Limitations of FPGA-based Virtual Hardware.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991
A Tag Coprocessor Architecture for Symbolic Languages.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Model-based fault diagnosis of sequential circuits and its acceleration.
Proceedings of the conference on European design automation, 1991


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