George A. Constantinides

According to our database1, George A. Constantinides authored at least 239 papers between 1982 and 2020.

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Bibliography

2020
architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute.
IEEE Trans. Very Large Scale Integr. Syst., 2020

LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference.
IEEE Trans. Computers, 2020

Approximate Logic Synthesis: A Survey.
Proc. IEEE, 2020

Horizon-independent Preconditioner Design for Linear Predictive Control.
CoRR, 2020

Digit Stability Inference for Iterative Methods Using Redundant Number Representation.
CoRR, 2020

Precise Pointer Analysis in High-Level Synthesis.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Combining Dynamic & Static Scheduling in High-level Synthesis.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
Automatic Software and Computing Hardware Codesign for Predictive Control.
IEEE Trans. Control. Syst. Technol., 2019

Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going.
ACM Comput. Surv., 2019

Rethinking Arithmetic for Deep Neural Networks.
CoRR, 2019

Bounding Computational Complexity under Cost Function Scaling in Predictive Control.
CoRR, 2019

Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization.
Proceedings of the International Conference on Field-Programmable Technology, 2019

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

LUTNet: Rethinking Inference in FPGA Soft Logic.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Modeling Round-off Error in the Fast Gradient Method for Predictive Control.
Proceedings of the 58th IEEE Conference on Decision and Control, 2019

A Probabilistic Approach to Floating-Point Arithmetic.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs.
ACM Trans. Reconfigurable Technol. Syst., 2018

Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware.
IEEE Trans. Computers, 2018

An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems.
Proceedings of the 8th International Joint Conference on Pervasive and Embedded Computing and Communication Systems, 2018

KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications.
Proceedings of the International Workshop on OpenCL, 2018

An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Concurrency-Aware Thread Scheduling for High-Level Synthesis.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Hardware Compilation of Deep Neural Networks: An Overview.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Digit Elision for Arbitrary-accuracy Iterative Computation.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

A High Throughput Polynomial and Rational Function Approximations Evaluator.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

2017
Certified Roundoff Error Bounds Using Semidefinite Programming.
ACM Trans. Math. Softw., 2017

Custom Multicache Architectures for Heap Manipulating Programs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications.
IEEE Des. Test, 2017

Automatic Software and Computing Hardware Co-design for Predictive Control.
CoRR, 2017

Nonlinear Predictive Control on a Heterogeneous Computing Platform.
CoRR, 2017

Automatically comparing memory consistency models.
Proceedings of the 44th ACM SIGPLAN Symposium on Principles of Programming Languages, 2017

Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs.
Proceedings of the International Conference on Field Programmable Technology, 2017

architect: Arbitrary-precision constant-hardware iterative compute.
Proceedings of the International Conference on Field Programmable Technology, 2017

Tile size selection for optimized memory reuse in high-level synthesis.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

STRIPE: Signal selection for runtime power estimation.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Hardware Synthesis of Weakly Consistent C Concurrency.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

FPGAs in the Cloud.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Quantifying error: Extending static timing analysis with probabilistic transitions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Algorithms and Arithmetic: Choose Wisely.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Separation Logic for High-Level Synthesis.
ACM Trans. Reconfigurable Technol. Syst., 2016

Balancing Locality and Concurrency: Solving Sparse Triangular Systems on GPUs.
Proceedings of the 23rd IEEE International Conference on High Performance Computing, 2016

An efficient implementation of online arithmetic.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A Case for Work-stealing on FPGAs with OpenCL Atomics.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Loop Splitting for Efficient Pipelining in High-Level Synthesis.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Multi-objective Co-design for model predictive control with an FPGA.
Proceedings of the 2016 European Control Conference, 2016

What is different about embedded optimization?
Proceedings of the 2016 European Control Conference, 2016

2015
Imprecise Datapath Design: An Overclocking Approach.
ACM Trans. Reconfigurable Technol. Syst., 2015

Communication Optimization of Iterative Sparse Matrix-Vector Multiply on GPUs and FPGAs.
IEEE Trans. Parallel Distributed Syst., 2015

A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic.
IEEE Trans. Computers, 2015

Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service.
CoRR, 2015

Custom-sized caches in application-specific memory hierarchies.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

PushPush: Seamless integration of hardware and software objects via function calls over AXI.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

MATCHUP: Memory Abstractions for Heap Manipulating Programs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Delay-Bounded Routing for Shadow Registers.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Numerical Program Optimization for High-Level Synthesis.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Fast FPGA prototyping toolbox for embedded optimization.
Proceedings of the European Control Conference, 2015

Transparent linking of compiled software and synthesized hardware.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Computer architectures to close the loop in real-time optimization.
Proceedings of the 54th IEEE Conference on Decision and Control, 2015

2014
Predictive Control Using an FPGA With Application to Aircraft Control.
IEEE Trans. Control. Syst. Technol., 2014

On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays.
IEEE Trans. Computers, 2014

Embedded Online Optimization for Model Predictive Control at Megahertz Rates.
IEEE Trans. Autom. Control., 2014

Mitigation of process variation effect in FPGAs with partial rerouting method.
IEICE Electron. Express, 2014

Classification on variation maps: a new placement strategy to alleviate process variation on FPGA.
IEICE Electron. Express, 2014

Constrained LQR for low-precision data representation.
Autom., 2014

Efficient FPGA implementation of digit parallel online arithmetic operators.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

FPGA implementation of an interior point method for high-speed model predictive control.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Area implications of memory partitioning for high-level synthesis on FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Compiling Higher Order Functional Programs to Composable Digital Hardware.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

GPU vs FPGA: A Comparative Analysis for Non-standard Precision.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
A Scalable Precision Analysis Framework.
IEEE Trans. Multim., 2013

Control-Theoretic Forward Error Analysis of Iterative Numerical Algorithms.
IEEE Trans. Autom. Control., 2013

Overclocking datapath for latency-error tradeoff.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

High-level synthesis of dynamic data structures: A case study using Vivado HLS.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

SOAP: Structural optimization of arithmetic expressions for high-level synthesis.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

FPGA-based K-means clustering using tree-based data structures.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

SMI: Slack Measurement Insertion for online timing monitoring in FPGAs.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A variation-adaptive retiming method exploiting reconfigurability.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Word-length optimization beyond straight line code.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Accuracy-Performance Tradeoffs on an FPGA through Overclocking.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Application Composition and Communication Optimization in Iterative Solvers Using FPGAs.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Energy-aware MPC co-design for DC-DC converters.
Proceedings of the European Control Conference, 2013

A predictive control solver for low-precision data representation.
Proceedings of the European Control Conference, 2013

Embedded Predictive Control on an FPGA using the Fast Gradient Method.
Proceedings of the European Control Conference, 2013

2012
Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms.
J. Signal Process. Syst., 2012

Optimizing Hardware Design by Composing Utility-Directed Transformations.
IEEE Trans. Computers, 2012

A Stable and Efficient Method for Solving a Convex Quadratic Program with Application to Optimal Control.
SIAM J. Optim., 2012

Analytical synthesis of bandwidth-efficient SDRAM address generators.
Microprocess. Microsystems, 2012

A sparse and condensed QP formulation for predictive control of LTI systems.
Autom., 2012

Correctly rounded constant integer division via multiply-add.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Enhancing performance of Tall-Skinny QR factorization using FPGAs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A two-stage variation-aware placement method for FPGAS exploiting variation maps classification.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A scalable approach for automated precision analysis.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Optimizing SDRAM bandwidth for custom FPGA loop accelerators.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Resource-Efficient Designs Using an Aspect-Oriented Approach.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Towards a fixed point QP solver for predictive control.
Proceedings of the 51th IEEE Conference on Decision and Control, 2012

FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods.
ACM Trans. Reconfigurable Technol. Syst., 2011

Bounding Variable Values and Round-Off Effects Using Handelman Representations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research.
IEEE Des. Test Comput., 2011

Numerical Data Representations for FPGA-Based Scientific Computing.
IEEE Des. Test Comput., 2011

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization.
Comput. J., 2011

An efficient algorithm for the solution of a coupled Sylvester equation appearing in descriptor systems.
Autom., 2011

A parallel formulation for predictive control with nonuniform hold constraints.
Annu. Rev. Control., 2011

Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

An FPGA implementation of a sparse quadratic programming solver for constrained predictive control.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Optimisation of mutually exclusive arithmetic sum-of-products.
Proceedings of the Design, Automation and Test in Europe, 2011

Parallel move blocking Model Predictive Control.
Proceedings of the 50th IEEE Conference on Decision and Control and European Control Conference, 2011

A condensed and sparse QP formulation for predictive control.
Proceedings of the 50th IEEE Conference on Decision and Control and European Control Conference, 2011

Solving a positive definite system of linear equations via the matrix exponential.
Proceedings of the 50th IEEE Conference on Decision and Control and European Control Conference, 2011

Accurate Floating Point Arithmetic through Hardware Error-Free Transformations.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Application Specific Memory Access, Reuse and Reordering for SDRAM.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays.
ACM Trans. Reconfigurable Technol. Syst., 2010

An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator.
ACM Trans. Reconfigurable Technol. Syst., 2010

A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices.
ACM Trans. Reconfigurable Technol. Syst., 2010

Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods.
ACM Trans. Reconfigurable Technol. Syst., 2010

FPGA Architecture Optimization Using Geometric Programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

FPGA implementation of an interior point solver for linear model predictive control.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A Scripting Engine for Combining Design Transformations.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Automated Precision Analysis: A Polynomial Algebraic Approach.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Customizable Composition and Parameterization of Hardware Design Transformations.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

A fast well-conditioned interior point method for predictive control.
Proceedings of the 49th IEEE Conference on Decision and Control, 2010

An ISS and l-stability approach to forward error analysis of iterative numerical algorithms.
Proceedings of the 49th IEEE Conference on Decision and Control, 2010

Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA.
Proceedings of the Reconfigurable Computing: Architectures, 2010

A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots.
J. Signal Process. Syst., 2009

Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2009

Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement.
ACM Trans. Reconfigurable Technol. Syst., 2009

Word-length selection for power minimization via nonlinear optimization.
ACM Trans. Design Autom. Electr. Syst., 2009

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems.
IET Comput. Digit. Tech., 2009

Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Area estimation and optimisation of FPGA routing fabrics.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Optimising designs by combining model-based and pattern-based transformations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control.
Proceedings of the FCCM 2009, 2009

Tutorial paper: Parallel architectures for model predictive control.
Proceedings of the European Control Conference, 2009

Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator.
Proceedings of the Reconfigurable Computing: Architectures, 2009

Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Guest Editorial: Field Programmable Technology.
J. Signal Process. Syst., 2008

Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection.
IEEE Trans. Circuits Syst. Video Technol., 2008

Custom parallel caching schemes for hardware-accelerated image compression.
J. Real Time Image Process., 2008

Glitch-aware output switching activity from word-level statistics.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Co-optimisation of datapath and memory in outer loop pipelining.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

A floating-point solver for band structured linear equations.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework.
Proceedings of the FPL 2008, 2008

An FPGA-based implementation of the MINRES algorithm.
Proceedings of the FPL 2008, 2008

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation.
Proceedings of the Visions of Computer Science, 2008

Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA.
Proceedings of the Reconfigurable Computing: Architectures, 2008

A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation.
Proceedings of the Reconfigurable Computing: Architectures, 2008

A Parallel Hardware Architecture for Image Feature Detection.
Proceedings of the Reconfigurable Computing: Architectures, 2008

FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Run-Time Integration of Reconfigurable Video Processing Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Special issue on Field-Programmable Technology.
J. Real Time Image Process., 2007

ROM to DSP block transfer for resource constrained synthesis.
IET Comput. Digit. Tech., 2007

CCDF and Monte Carlo Analysis of a Digital Polar Transmitter for Ultra-Wideband System.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

On the feasibility of early routing capacitance estimation for FPGAs.
Proceedings of the FPL 2007, 2007

Automatic On-chip Memory Minimization for Data Reuse.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

A Hybrid Memory Sub-system for Video Coding Applications.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
Word-length optimization for differentiable nonlinear systems.
ACM Trans. Design Autom. Electr. Syst., 2006

Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Accuracy-Guaranteed Bit-Width Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

On-Chip Communication in Run-Time Assembled Reconfigurable Systems.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Fast word-level power models for synthesis of FPGA-based arithmetic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Modeling of glitch effects in FPGA based arithmetic circuits.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

PowerBit - power aware arithmetic bit-width optimization.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

An FPGA implementation of the simplex algorithm.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

The cost of data dependence in motion vector estimation for reconfigurable platforms.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Dynamic Memory Sub-System for Reconfigurable Platforms.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Yield enhancements of design-specific FPGAs.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

A Flexible Multi-port Caching Scheme for Reconfigurable Platforms.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Optimum and heuristic synthesis of multiple word-length architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A heuristic approach for multiple restricted multiplication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel 2D filter design methodology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An Analytical Approach to Generation and Exploration of Reconfigurable Architectures.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Power and Area Optimization for Multiple Restricted Multiplication.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

FPGA-Accelerated Reconstruction of Gene Regulatory Networks.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Parameterized Logic Power Consumption Models for FPGA based Systems.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Heterogeneity Exploration for Multiple 2D Filter Designs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Exploration of heterogeneous reconfigurable architectures (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

A Novel 2D Filter Design Methodology for Heterogeneous Devices.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004
Guest Editors' Introduction: Field Programmable Logic and Applications.
IEEE Trans. Computers, 2004

Multiple Restricted Multiplication.
Proceedings of the Field Programmable Logic and Application, 2004

A Structured Methodology for System-on-an-FPGA Design.
Proceedings of the Field Programmable Logic and Application, 2004

Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation.
Proceedings of the Field Programmable Logic and Application, 2004

A Structured System Methodology for FPGA Based System-on-A-Chip Design.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Migrating Functionality from ROMS to Embedded Multipliers.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Word-Length Optimization of Folded Polynomial Evaluation.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Synthesis and optimization of DSP algorithms.
Kluwer, ISBN: 978-1-4020-7930-6, 2004

2003
Synthesis of saturation arithmetic architectures.
ACM Trans. Design Autom. Electr. Syst., 2003

Wordlength optimization for linear digital signal processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Review of Computer arithmetic algorithms by Israel Koren. A.K. Peters.
SIGACT News, 2003

Architectures for function evaluation on FPGAs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A Reconfigurable Platform for Real-Time Embedded Video Image Processing.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Perturbation Analysis for Word-length Optimization.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

2002
The complexity of multiple wordlength assignment.
Appl. Math. Lett., 2002

Strassen's matrix multiplication for customisable processors.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Optimum Wordlength Allocation.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
The Multiple Wordlength Paradigm.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Heuristic datapath allocation for multiple wordlength systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Active filter synthesis based on tuneable log-domain lossy integrators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Roundoff-noise shaping in filter design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Multiple-Wordlength Resource Binding.
Proceedings of the Field-Programmable Logic and Applications, 2000

Multiple Precision for Resource Minimization.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
<i>Synthia</i>: Synthesis of Interacting Automata Targeting LUT-based FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1991
Layered DCT video coding for embedded data transmission over BISDN.
Proceedings of the 1991 International Conference on Acoustics, 1991

1983
Maximum likelihood estimation of composite source models for image coding.
Proceedings of the IEEE International Conference on Acoustics, 1983

1982
Composite source coding techniques for image bandwidth compression.
Proceedings of the IEEE International Conference on Acoustics, 1982


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