Jongwoo Bae

According to our database1, Jongwoo Bae authored at least 19 papers between 1994 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2014
High-Throughput Parallel Architecture for H.265/HEVC Deblocking Filter.
J. Inf. Sci. Eng., 2014

2013
High-Performance VLSI Architecture of H.264/AVC CAVLD by Parallel Run_before Estimation Algorithm.
J. Inf. Sci. Eng., 2013

Geometric Image Compensation Method for a Portable Projector Based on Rewarping Using 2D Homography.
KSII Trans. Internet Inf. Syst., 2013

Register array-based VLSI architecture of H.265/HEVC loop filter.
IEICE Electron. Express, 2013

Performance Optimization of Aho-Corasick Algorithm on a GPU.
Proceedings of the 12th IEEE International Conference on Trust, 2013

2011
High performance VLSI design of run_before for H.264/AVC CAVLD.
IEICE Electron. Express, 2011

2009
Parallel implementation of a financial application on a GPU.
Proceedings of the 2nd International Conference on Interaction Sciences: Information Technology, 2009

2008
Color transient improvement with transient detection and variable length nonlinear filtering.
IEEE Trans. Consumer Electron., 2008

A decoupled architecture for multi-format decoder.
IEICE Electron. Express, 2008

2007
Quarter-pel Interpolation Architecture in H.264/AVC Decoder.
Proceedings of the 2007 International Conference on Intelligent Pervasive Computing, 2007

2006
Edge-adaptive local min/max nonlinear filter-based shoot suppression.
IEEE Trans. Consumer Electron., 2006

Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

1998
Synthesis of area-efficient and high-throughput rate data format converters.
IEEE Trans. Very Large Scale Integr. Syst., 1998

1996
Synthesis of VLSI architectures for tree-structured image coding.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

Synthesis of memory-based VLSI architectures for discrete wavelet transforms.
Proceedings of the 8th European Signal Processing Conference, 1996

1995
A fast and area-efficient VLSI architecture for embedded image coding.
Proceedings of the Proceedings 1995 International Conference on Image Processing, 1995

Synthesis of VLSI Architectures for Two-Dimensional Discrete Wavelet Transforms.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
A General Framework for Synthesis of Data Format Converters.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Synthesis of a class of data format converters with specified delays.
Proceedings of the International Conference on Application Specific Array Processors, 1994


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