Jörg Behrend

According to our database1, Jörg Behrend authored at least 13 papers between 2007 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2017
Optimized hybrid verification of embedded software.
PhD thesis, 2017

2015
Scalable and Optimized Hybrid Verification of Embedded Software.
J. Electron. Test., 2015

2014
LoCEG: Local Preprocessing in SAT-Solving through Counter-Example Generation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Optimized hybrid verification of embedded software.
Proceedings of the 15th Latin American Test Workshop, 2014

2012
Optimized Static Parameter Assignment for Semiformal Software Verification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

2011
DWARF-driven Equivalence Checking of UML Statecharts and Software Components.
Softwaretechnik-Trends, 2011

Scalable and Extendable Hybrid Verification Platform.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Scalable hybrid verification for embedded software.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
State-based Analysis and UML-driven Equivalence Checking for C++ State Machines.
Proceedings of the FM+AM 2010, 2010

2009
Semiformal verification of temporal properties in automotive hardware dependent software.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Object-Oriented Message-Passing in Heterogeneous Environments.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 2008

2007
UML/SysML-Systemanalyse zur Generierung von formalen Verifikationseigenschaften für verschiedene Abstraktionsebenen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Grid Based Fast Falsification For Bounded Property Checking.
Proceedings of the Forum on specification and Design Languages, 2007


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