Jürgen Ruf

Affiliations:
  • University of Tübingen, Wilhelm-Schickard-Institute for Computer Science, Germany
  • IBM Systems and Technology Group, Boeblingen, Germany


According to our database1, Jürgen Ruf authored at least 65 papers between 1997 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2017
Using Robustness Testing to Handle Incomplete Verification Results When Combining Verification and Testing Techniques.
Proceedings of the Testing Software and Systems, 2017

2015
Scalable and Optimized Hybrid Verification of Embedded Software.
J. Electron. Test., 2015

Efficient Testing of Different Loop Paths.
Proceedings of the Software Engineering and Formal Methods - 13th International Conference, 2015

Efficient Fault Localization During Replay of Embedded Software.
Proceedings of the 41st Euromicro Conference on Software Engineering and Advanced Applications, 2015

2014
More Flexible Object Invariants with Less Specification Overhead.
Proceedings of the Software Engineering and Formal Methods - 12th International Conference, 2014

Increasing Software Reliability by Integrating Formal Verification and Robustness Testing.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Erkennen von Speicherverletzungen im Testbetrieb von eingebetteter Software.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

LoCEG: Local Preprocessing in SAT-Solving through Counter-Example Generation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Optimized hybrid verification of embedded software.
Proceedings of the 15th Latin American Test Workshop, 2014

Debugger-Based Record Replay and Dynamic Analysis for In-Vehicle Infotainment.
Proceedings of the Computational Science and Its Applications - ICCSA 2014 - 14th International Conference, Guimarães, Portugal, June 30, 2014

2013
A Software Testing Framework to Integrate Formal Verification Results.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Beschleunigte Robustheitstests für verhaltensbeschreibende Zustandsmaschinen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

2012
Optimized Static Parameter Assignment for Semiformal Software Verification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

2011
DWARF-driven Equivalence Checking of UML Statecharts and Software Components.
Softwaretechnik-Trends, 2011

Scalable and Extendable Hybrid Verification Platform.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Scalable hybrid verification for embedded software.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
State-based Analysis and UML-driven Equivalence Checking for C++ State Machines.
Proceedings of the FM+AM 2010, 2010

Towards assertion-based verification of heterogeneous system designs.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Design and verification of the IBM System z10 I/O subsystem chips.
IBM J. Res. Dev., 2009

Semiformal verification of temporal properties in automotive hardware dependent software.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Advanced Assertion-Based Design for Mixed-Signal Verification.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Verification of Temporal Properties in Automotive Embedded Software.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Semiformal Verification of Temporal Properties in Embedded Software.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

UML/SysML-Systemanalyse zur Generierung von formalen Verifikationseigenschaften für verschiedene Abstraktionsebenen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Transaction Modeling and RTL Simulation Analysis.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Coverage Driven Verification applied to Embedded Software.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Grid Based Fast Falsification For Bounded Property Checking.
Proceedings of the Forum on specification and Design Languages, 2007

2006
Automatische Eigenschaftsextraktion auf Systemebene aus SystemC Modellen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Monitoring-based Formal Hardware Verification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Fast falsification based on symbolic bounded property checking.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Distributed Symbolic Bounded Property Checking.
Proceedings of the 4th International Workshop on Parallel and Distributed Methods in Verification, 2005

Overlap reduction in symbolic system traversal.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Efficient and Customizable Integration of Temporal Properties.
Proceedings of the Forum on specification and Design Languages, 2005

2004
Transactional Level Verification and Coverage Metrics by Means of Symbolic Simulation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Dynamic guiding of bounded property checking.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Modeling and Formal Verification of Production Automation Systems.
Proceedings of the Integration of Software Specification Techniques for Applications in Engineering, 2004

Specification and Formal Verification of Temporal Properties of Production Automation Systems.
Proceedings of the Integration of Software Specification Techniques for Applications in Engineering, 2004

2003
Optimized Temporal Logic Compilation.
J. Univers. Comput. Sci., 2003

Symbolic Verification and Analysis of Discrete Timed Systems.
Formal Methods Syst. Des., 2003

Bounded Property Checking with Symbolic Simulation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Using Symbolic Simulation for Bounded Property Checking.
Proceedings of the Forum on specification and Design Languages, 2003

2002
Combination of Simulation and Formal Verification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

A Visual Approach to Validating System Level Designs.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Formal Data Analysis of Timed Finite State Systems.
Proceedings of the 14th Euromicro Conference on Real-Time Systems (ECRTS 2002), 2002

2001
RAVEN: Real-Time Analyzing and Verification Environment.
J. Univers. Comput. Sci., 2001

Correctness of Efficient Real-Time Model Checking.
J. Univers. Comput. Sci., 2001

Formale Verifikation diskreter Echtzeitsysteme (Formal Verification of Discrete Real-Time Systems).
Informationstechnik Tech. Inform., 2001

Customer-Oriented Systems Design through Virtual Prototypes.
Proceedings of the 10th IEEE International Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprises (WETICE 2001), 2001

Data Analysis of Timed Finite State Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Simulation-guided property checking based on a multi-valued AR-automata.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

The simulation semantics of systemC.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Techniken zur Modellierung und Verifikation von Echtzeitsystemen.
PhD thesis, 2000

A Toolset for the Symbolic Examination of Finite State Transition Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

Structured English for Model Checking Specification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

Checking temporal properties under simulation of executable system descriptions.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Do You Trust Your Model Checker?
Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

Simulation Meets Verification: Checking Temporal Properties in SystemC.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Analyzing Real-Time Systems.
Proceedings of the 2000 Design, 2000

1999
Modeling Real-Time Systems with I/O-Interval Structures.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

Modleing and Checking Networks of Communicating Real-Time Process.
Proceedings of the Correct Hardware Design and Verification Methods, 1999

1998
A Synchronous Language for Modeling and Verifying Real Time and Embedded Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1998

Using MTBDDs for Compostion and Model Checking of Real-Time Systems.
Proceedings of the Formal Methods in Computer-Aided Design, 1998

1997
A New Algorithm for Discrete Timed Symbolic Model Checking.
Proceedings of the Hybrid and Real-Time Systems, 1997

Using MTBDDs for discrete timed symbolic model checking.
Proceedings of the European Design and Test Conference, 1997

Symbolic model checking for a discrete clocked temporal logic with intervals.
Proceedings of the Advances in Hardware Design and Verification, 1997


  Loading...