Pradeep Kumar Nalla

According to our database1, Pradeep Kumar Nalla authored at least 13 papers between 2005 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2016
FVCAG: A framework for formal verification driven power modeling and verification.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

The art of semi-formal bug hunting.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2014
Effective Liveness Verification Using a Transformation-Based Framework.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
GLA: gate-level abstraction revisited.
Proceedings of the Design, Automation and Test in Europe, 2013

2009
Semiformal verification of temporal properties in automotive hardware dependent software.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Efficient distributed bounded property checking.
PhD thesis, 2008

Design of Concurrent Utilities in Jackal: A Software DSM Implementation.
Proceedings of the Distributed Computing and Networking, 9th International Conference, 2008

Verification of Temporal Properties in Automotive Embedded Software.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Semiformal Verification of Temporal Properties in Embedded Software.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Grid Based Fast Falsification For Bounded Property Checking.
Proceedings of the Forum on specification and Design Languages, 2007

2006
Fast falsification based on symbolic bounded property checking.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Distributed Symbolic Bounded Property Checking.
Proceedings of the 4th International Workshop on Parallel and Distributed Methods in Verification, 2005

Overlap reduction in symbolic system traversal.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005


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