Joseph Callenes

According to our database, Joseph Callenes authored at least 24 papers between 2014 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A Multidisciplinary Framework for using emerging Computing Systems in Engineering Education.

Joseph Callenes, Tan Run En, Aria Pegah

Proceedings of the IEEE Frontiers in Education Conference, 2022

Tiny Black Boxes: A nano-Drone Safety Architecture.

Connor Sexton, Joseph Callenes

Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

2021

Heterogeneous System Model for Security in E-Health Applications.

Isabel Jellen, Joseph Callenes-Sloan, Dongfeng Fang

Proceedings of the IEEE International Conference on Communications Workshops, 2021

A Dynamic Reconfiguration-based Approach to Resilient State Estimation.

Annie Joss, Austin Grassbaugh, Majid Poshtan, Joseph Callenes

Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2021

2020

Using Power Infrastructures for Wildfire Detection in California.

Emil Erickson, Reed Slobodin, Majid Poshtan, Taufik Taufik, Joseph Callenes

Proceedings of the IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2020

In Depth Exploration of Added Course Expenses on Students of Various Socioeconomic Status.

Andrew Danowitz, Bridget Benson, Paul Hummel, Joseph Callenes, K. Clay McKell

Proceedings of the IEEE Frontiers in Education Conference, 2020

2019

Impact of Cyber-Attacks on Power Grids with Distributed Energy Storage Systems.

Michael Tuttle, Majid Poshtan, Taufik Taufik, Joseph Callenes

Proceedings of the 2019 IEEE International Conference on Communications, 2019

Algorithmic Approaches to Characterizing Power Flow Cyber-Attack Vulnerabilities.

Michael Tuttle, Braden Wicker, Majid Poshtan, Joseph Callenes

Proceedings of the IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2019

Repurposing Retired Faculty Laptops to Make Engineering More Accessible.

Andrew Danowitz, K. Clay McKell, Bridget Benson, Joseph Callenes, Paul Hummel, Robert Randall

Proceedings of the IEEE Frontiers in Education Conference, 2019

2018

Control Flow Checking Optimization Based on Regular Patterns Analysis.

Zhiqi Zhu, Joseph Callenes-Sloan, Benjamin Carrión Schäfer

Proceedings of the 23rd IEEE Pacific Rim International Symposium on Dependable Computing, 2018

Optimizing energy in a DRAM based hybrid cache.

Jiacong He, Joseph Callenes-Sloan

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Treety: A Data-driven Approach to Urban Canopy Development.

Sonia Mannan, Joseph Callenes-Sloan

Proceedings of the IEEE International Smart Cities Conference, 2018

Differences in Mental Health between Students in a Jointly Offered Computer Engineering Program and the two Home Departments.

Andrew Danowitz, Bridget Benson, Joseph Callenes-Sloan, Paul Hummel

Proceedings of the IEEE Frontiers in Education Conference, 2018

Exploring the Relevance and Energy Usage Implications of Fixed Computer Labs in Electrical Engineering Education.

Joseph Callenes-Sloan, Paul Hummel, Andrew Danowitz, Bridget Benson

Proceedings of the IEEE Frontiers in Education Conference, 2018

A machine learning based hard fault recuperation model for approximate hardware accelerators.

Farah Naz Taher, Joseph Callenes-Sloan, Benjamin Carrión Schäfer

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

A Novel Architecture of Large Hybrid Cache With Reduced Energy.

Jiacong He, Joseph Callenes-Sloan

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Designing large hybrid cache for future HPC systems.

Jiacong He, Joseph Callenes-Sloan

Proceedings of the 25th High Performance Computing Symposium, Virginia Beach, VA, USA, April 23, 2017

A software-defined hybrid cache with reduced energy: poster.

Jiacong He, Joseph Callenes-Sloan

Proceedings of the 18th ACM/IFIP/USENIX Middleware Conference: Posters and Demos, Las Vegas, NV, USA, December 11, 2017

TCache: An energy-efficient DRAM cache design.

Jiacong He, Joseph Callenes-Sloan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Architecting a Novel Hybrid Cache with Low Energy.

Jiacong He, Joseph Callenes-Sloan

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Reducing the energy of a large hybrid cache.

Jiacong He, Joseph Callenes-Sloan

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Towards low overhead control flow checking using regular structured control.

Zhiqi Zhu, Joseph Callenes-Sloan

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Hardware Fault Compensation Using Discriminative Learning.

Farah Naz Taher, Joseph Callenes-Sloan

Proceedings of the 21st IEEE Pacific Rim International Symposium on Dependable Computing, 2015

2014

Algorithm Selection for Error Resilience in Scientific Computing.

Joseph Callenes-Sloan, Hugh McNamara

Proceedings of the 20th IEEE Pacific Rim International Symposium on Dependable Computing, 2014