Jason Kamran Eshraghian

According to our database1, Jason Kamran Eshraghian authored at least 81 papers between 1988 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A Novel Universal Interface for Constructing Memory Elements for Circuit Applications.
IEEE Trans. on Circuits and Systems, 2019

Adaptive Precision CNN Accelerator Using Radix-X Parallel Connected Memristor Crossbars.
CoRR, 2019

Adaptive Precision CNN Accelerator Using Radix-X Parallel Connected Memristor Crossbars.
CoRR, 2019

Analog Weights in ReRAM DNN Accelerators.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Neuromorphic Vision Hybrid RRAM-CMOS Architecture.
IEEE Trans. VLSI Syst., 2018

Neuromorphic Vision Hybrid RRAM-CMOS Architecture.
IEEE Trans. VLSI Syst., 2018

Formulation and Implementation of Nonlinear Integral Equations to Model Neural Dynamics Within the Vertebrate Retina.
Int. J. Neural Syst., 2018

Formulation and Implementation of Nonlinear Integral Equations to Model Neural Dynamics Within the Vertebrate Retina.
Int. J. Neural Syst., 2018

2017
Maximization of Crossbar Array Memory Using Fundamental Memristor Theory.
IEEE Trans. on Circuits and Systems, 2017

Maximization of Crossbar Array Memory Using Fundamental Memristor Theory.
IEEE Trans. on Circuits and Systems, 2017

Biological modeling of vertebrate retina: Rod cell to bipolar cell.
Proceedings of the 40th International Conference on Telecommunications and Signal Processing, 2017

Biological modeling of vertebrate retina: Rod cell to bipolar cell.
Proceedings of the 40th International Conference on Telecommunications and Signal Processing, 2017

2016
Modelling and characterization of dynamic behavior of coupled memristor circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Modelling and analysis of signal flow platform implementation into retinal cell pathway.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Modelling and analysis of signal flow platform implementation into retinal cell pathway.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Live demonstration: Signal flow platform implementation into retinal cell pathway.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Live demonstration: Signal flow platform implementation into retinal cell pathway.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Memristor-CMOS logic and digital computational components.
Microelectronics Journal, 2015

2014
High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture.
IEEE Trans. VLSI Syst., 2014

2013
Complementary Resistive Switch (CRS) based smart sensor search engine.
Proceedings of the 2013 IEEE Eighth International Conference on Intelligent Sensors, 2013

2012
Memristive Device Fundamentals and Modeling: Applications to Circuits and Systems Simulation.
Proceedings of the IEEE, 2012

Live demonstration: High fill factor CIS based on single inverter architecture.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines.
IEEE Trans. VLSI Syst., 2011

Memristor-based Synaptic Networks and Logical Operations Using In-Situ Computing
CoRR, 2011

An Analytical Approach for Memristive Nanoarchitectures
CoRR, 2011

2010
3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications.
IEEE Trans. Biomed. Circuits and Systems, 2010

2009
System-on-System (SoS) architecture for 3-D secure imaging.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
"Surfing the iSoC multitechnology platform: Volumetric growth beyond Moore's law".
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

2006
SoC Emerging Technologies.
Proceedings of the IEEE, 2006

3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems.
EURASIP J. Adv. Sig. Proc., 2006

2005
3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

2004
Integrated Optical Routing Topology for MicroPhotonic Switches.
Proceedings of the High Speed Networks and Multimedia Communications, 2004

High Density and Low Power Beam Steering Opto-ULSI Processor for IIPS.
Proceedings of the High Speed Networks and Multimedia Communications, 2004

Reconfigurable Add/Drop Multiplexing Topology Employing Adaptive MicroPhotonic Technology.
Proceedings of the High Speed Networks and Multimedia Communications, 2004

Novel Integrated Optical Router for MicroPhotonic Switching.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Multi-band MicroPhotonic Tunable Optical Filter.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Dynamic MicroPhotonic WDM Equalizer.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

A Novel Design of Beam Steering n-phase OPTO-ULSI Processor for IIPS.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

SOC-B Design and Testing Technique of IS-95C CDMA Transmitter for Measurement of Electric Field Intensity using FPGA and ASIC.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Pixel Structure Effects on Crosstalk in Backwall Illuminated CMOS Compatible Photodiode Arrays.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Integrated MicroPhotonic Broadband Smart Antenna Beamformer.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Integrated MicroPhotonic Wideband RF Interference Mitigation Filter.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

MicroPhotonic Reconfigurable RF Signal Processor.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Reconfigurable MicroPhotonic Add/Drop Multiplexer Architecture.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Testing and Analysis of Computer Generated Holograms for MicroPhotonic Devices.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2001
Knowledge-based Genetic Algorithm for Layer Assignment.
Proceedings of the 24th Australasian Computer Science Conference (ACSC 2001), 29 January, 2001

2000
CMOS circuit for high-speed flexible read-out of CMOS imagers.
Proceedings of the Visual Communications and Image Processing 2000, 2000

Deep Submicron USLI Design Paradigm: Who is Writing the Future?
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A high fill-factor native logarithmic pixel: Simulation, design and layout optimization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A dataflow-oriented VLSI architecture for a modified SPIHT algorithm using depth-first search bit stream processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Improving Binary Compatibility in VLIW Machines through Compiler Assisted Dynamic Rescheduling.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm.
Proceedings of the 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January, 2000

1999
System analysis of an intelligent pixel mobile multimedia communicator.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

Massively parallel wavelet based video codec for an intelligent-pixel mobile multimedia communicator.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

Self-timed MESFET gallium arsenide circuit techniques for a direct digital frequency synthesiser.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

Smart pixel VLSI architecture for embedded zerotree wavelet coding.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

Robust image compression using the depth-first search on the wavelet zerotree.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

EZW algorithm using depth-first representation of the wavelet zerotree.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

VLSI decoder architecture for embedded zerotree wavelet algorithm.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications.
Proceedings of the VLSI: Systems on a Chip, 1999

Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI.
Proceedings of the VLSI: Systems on a Chip, 1999

Low Power Techniques for Digital GaAs VLSI.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
A parameter search technique to build an ARMA model.
Proceedings of the Knowledge-Based Intelligent Electronic Systems, 1998

Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications.
Proceedings of the 1998 Design, 1998

1997
A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin's Asynchronous Design Methodology.
IEEE Trans. Computers, 1997

An Asynchronous Morphological Processor for Multi-Media Applications.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Opto-VLSI Systems for Multimedia Computing.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Dynamic hazards and speed independent delay model.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
Biologically inspired obstacle avoidance - a technology independent paradigm.
Proceedings of the Mobile Robots X, Philadephia, PA, USA, October 23, 1995, Proceedings, 1995

Feature Representation of Motion Trajectories.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

The impact of VLSI technologies on neural networks.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

A robust adaptive sliding mode tracking control using an RBF neural network for robotic manipulators.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

An adaptive tracking controller using neural networks for nonlinear systems.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

Multiplicative noise cancellation (MNC) in analog VLSI vision sensors.
Proceedings of the Electronic Technology Directions to the Year 2000, 1995

A 32-bit GaAs IEEE floating point multiplier using Trailing-1's rounding algorithm.
Proceedings of the Electronic Technology Directions to the Year 2000, 1995

A GaAs IEEE Floating Point Standard Single Precision Multiplier.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994
Dual-Purpose Interpretation of Sensory Information.
Proceedings of the 1994 International Conference on Robotics and Automation, 1994

Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide Technology.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1988
Basic VLSI design - systems and circuits (2. ed.).
Prentice Hall Silicon Systems Engineering Series, Prentice Hall, ISBN: 978-0-7248-0105-3, 1988


  Loading...