Joseph J. Sharkey

According to our database, Joseph J. Sharkey authored at least 20 papers between 2004 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Selective Writeback: Reducing Register File Pressure and Energy Consumption.

Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose

IEEE Trans. Very Large Scale Integr. Syst., 2008

Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption.

Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose

IEEE Trans. Computers, 2008

Reducing register pressure in SMT processors through L2-miss-driven early register release.

Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev

ACM Trans. Archit. Code Optim., 2008

Hiding Communication Delays in Clustered Microarchitectures.

Robert J. LaDuca, Joseph J. Sharkey, Dmitry V. Ponomarev

Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

2007

Exploiting Operand Availability for Efficient Simultaneous Multithreading.

Joseph J. Sharkey, Dmitry V. Ponomarev

IEEE Trans. Computers, 2007

Evaluating design tradeoffs in on-chip power management for CMPs.

Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

An L2-miss-driven early register deallocation for SMT processors.

Joseph J. Sharkey, Dmitry V. Ponomarev

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2006

Instruction packing: Toward fast and energy-efficient instruction scheduling.

Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin

ACM Trans. Archit. Code Optim., 2006

Selective writeback: exploiting transient values for energy-efficiency and performance.

Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch.

Joseph J. Sharkey, Dmitry Ponomarev

Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

Address-Value Decoupling for Early Register Deallocation.

Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Aneesh Aggarwal

Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

Efficient instruction schedulers for SMT processors.

Joseph J. Sharkey, Dmitry V. Ponomarev

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors.

Joseph J. Sharkey, Nayef Abu-Ghazeleh, Dmitry V. Ponomarev, Kanad Ghose, Aneesh Aggarwal

Proceedings of the High Performance Computing, 2006

Adaptive reorder buffers for SMT processors.

Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency.

Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

Instruction packing: reducing power and delay of the dynamic scheduling logic.

Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Power-Efficient Wakeup Tag Broadcast.

Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Instruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers.

Joseph J. Sharkey, Dmitry V. Ponomarev

Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

Non-uniform Instruction Scheduling.

Joseph J. Sharkey, Dmitry V. Ponomarev

Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

2004

Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization.

Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin

Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004