Pradip Bose

According to our database1, Pradip Bose authored at least 176 papers between 1982 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2007, "For contributions to power modeling and processor design".

Timeline

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Bibliography

2020
MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing.
CoRR, 2020

STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.
CoRR, 2020

Asymmetric Resilience: Exploiting Task-Level Idempotency for Transient Error Recovery in Accelerator-Based Systems.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
Energy-Secure System Architectures (ESSA): A Workshop Report.
IEEE Micro, 2019

Asymmetric Resilience for Accelerator-Rich Systems.
IEEE Comput. Archit. Lett., 2019

Resilient Low Voltage Accelerators for High Energy Efficiency.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Generation of Stressmarks for Early Stage Soft-Error Modeling.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Towards "Smarter" Vehicles Through Cloud-Backed Swarm Cognition.
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018

ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

Impact of Software Approximations on the Resiliency of a Video Summarization System.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2018

Energy-secure swarm power management.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Architectural Support for Cognitive Processing.
IEEE Micro, 2017

Machine learning techniques for taming the complexity of modern hardware design.
IBM J. Res. Dev., 2017

Mitigating Power Contention: A Scheduling Based Approach.
IEEE Comput. Archit. Lett., 2017

Invited paper: Secure swarm intelligence: A new approach to many-core power management.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Invited paper: Resilient and energy-secure power management.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

libPRISM: an intelligent adaptation of prefetch and SMT levels.
Proceedings of the International Conference on Supercomputing, 2017

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017


BRAVO: Balanced Reliability-Aware Voltage Optimization.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Special issue on energy efficient methods and systems in the emerging cloud era.
J. Comput. Syst. Sci., 2016

New Frontiers in Energy-Efficient Computing [Guest editors' introduction].
Computer, 2016

Understanding error propagation in GPGPU applications.
Proceedings of the International Conference for High Performance Computing, 2016

Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Resilience characterization of a vision analytics application under varying degrees of approximation.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Characterization and mitigation of power contention across multiprogrammed workloads.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Robust power management in the IBM z13.
IBM J. Res. Dev., 2015

Active Memory Cube: A processing-in-memory architecture for exascale systems.
IBM J. Res. Dev., 2015

Understanding the propagation of transient errors in HPC applications.
Proceedings of the International Conference for High Performance Computing, 2015

Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Experience report: An application-specific checkpointing technique for minimizing checkpoint corruption.
Proceedings of the 26th IEEE International Symposium on Software Reliability Engineering, 2015

Power-efficient embedded processing with resilience and real-time constraints.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Resilient mobile cognition: Algorithms, innovations, and architectures.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Resilient, UAV-embedded real-time computing.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Quantifying sources of error in McPAT and potential impacts on architectural studies.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Increasing multicore system efficiency through intelligent bandwidth shifting.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
Adaptive Prefetching on POWER7: Improving Performance and Power Consumption.
ACM Trans. Parallel Comput., 2014

Special Series on Harsh Chips [Guest editors' introduction].
IEEE Micro, 2014

Addressing failures in exascale computing.
Int. J. High Perform. Comput. Appl., 2014

The resilience wall: Cross-layer solution strategies.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Understanding Soft Error Resiliency of Blue Gene/Q Compute Chip through Hardware Proton Irradiation and Software Fault Injection.
Proceedings of the International Conference for High Performance Computing, 2014

Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Energy-secure computer architectures.
Proceedings of the 2014 International Test Conference, 2014

Empirically derived abstractions in uncore power modeling for a server-class processor chip.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Characterization of transient error tolerance for a class of mobile embedded applications.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

3D stacking of high-performance processors.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
SMT Malleability in IBM POWER5 and POWER6 Processors.
IEEE Trans. Computers, 2013

Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems.
IBM J. Res. Dev., 2013

SMT Switch: Software Mechanisms for Power Shifting.
IEEE Comput. Archit. Lett., 2013

Is dark silicon real?: technical perspective.
Commun. ACM, 2013

Crank it up or dial it down: coordinated multiprocessor frequency and folding control.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Keynote address thursday: Efficient resilience in future systems: Design and modeling challenges.
Proceedings of the 2013 IEEE International Test Conference, 2013

SMT-centric power-aware thread placement in chip multiprocessors.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Energy-aware meeting scheduling algorithms for smart buildings.
Proceedings of the BuildSys '12 Proceedings of the Fourth ACM Workshop on Embedded Sensing Systems for Energy-Efficiency in Buildings, 2012

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Energy-secure computing.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Power management of multi-core chips: Challenges and pitfalls.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Making data prefetch smarter: adaptive prefetching on POWER7.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Power Wall.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Error Tolerance in Server Class Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Energy-Aware Accounting and Billing in Large-Scale Computing Facilities.
IEEE Micro, 2011

Introducing the Adaptive Energy Management Features of the Power7 Chip.
IEEE Micro, 2011

Adaptive energy-management features of the IBM POWER7 chip.
IBM J. Res. Dev., 2011

Characterizing Power and Temperature Behavior of POWER6-Based System.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Curbing energy cravings in networks: A cross-sectional view across the micro-macro boundary.
Proceedings of the NOCS 2011, 2011

Keynote II: Integrated modeling challenges in extreme-scale computing.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

A case for guarded power gating for multi-core processors.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Abstraction and microarchitecture scaling in early-stage power modeling.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Variation-Tolerant Microprocessor Architecture at Low Power.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
Trends and techniques for energy efficient architectures.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Guarded Power Gating in a Multi-core Setting.
Proceedings of the Computer Architecture, 2010

Power-efficient, reliable microprocessor architectures: modeling and design methods.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Performance and power evaluation of an in-line accelerator.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Power and thermal characterization of POWER6 system.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design.
IEEE Des. Test Comput., 2009

Tribeca: design for PVT variations with local recovery and fine-grained adaptation.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Multicore power management: Ensuring robustness via early-stage formal verification.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Dynamic power gating with quality guarantees.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
Phaser: Phased methodology for modeling the system-level effects of soft errors.
IBM J. Res. Dev., 2008

Metrics for Architecture-Level Lifetime Reliability Analysis.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Online Estimation of Architectural Vulnerability Factor for Soft Errors.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Exploring power management in multi-core systems.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop.
SIGARCH Comput. Archit. News, 2007

Low-Power Design and Temperature Management.
IEEE Micro, 2007

Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements.
IEEE J. Solid State Circuits, 2007

Temperature-limited microprocessors: Measurements and design implications.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Evaluating design tradeoffs in on-chip power management for CMPs.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Thermal-aware task scheduling at the system software level.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A Framework for Architecture-Level Lifetime Reliability Modeling.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Performance modeling for early analysis of multi-core systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Looking briefly back, and then forward...
IEEE Micro, 2006

Designing reliable systems with unreliable components.
IEEE Micro, 2006

Pre-Silicon Modeling and Analysis: Impact On Real Design.
IEEE Micro, 2006

Robust On-Chip Communication.
IEEE Micro, 2006

Workload characterization: A key aspect of microarchitecture design.
IEEE Micro, 2006

Measuring the impact of microarchitectural ideas.
IEEE Micro, 2006

An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

2005
Guest Editors' Introduction: Energy-Efficient Design.
IEEE Micro, 2005

Lifetime Reliability: Toward an Architectural Solution.
IEEE Micro, 2005

Designing microprocessors with robust functionality and performance.
IEEE Micro, 2005

High performance at affordable power.
IEEE Micro, 2005

Presilicon modeling: challenges in the late CMOS era.
IEEE Micro, 2005

Integrated microarchitectures.
IEEE Micro, 2005

Variation-tolerant design.
IEEE Micro, 2005

The "power" of communication.
IEEE Micro, 2005

Power-Aware, Reliable Microprocessor Design.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Exploiting Structural Duplication for Lifetime Reliability Enhancement.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

2004
Integrated Analysis of Power and Performance for Pipelined Microprocessors.
IEEE Trans. Computers, 2004

Power-performance simulation: design and validation strategies.
SIGMETRICS Perform. Evaluation Rev., 2004

Computer architecture research: Shifting priorities and newer challenges.
IEEE Micro, 2004

Communication versus Computation.
IEEE Micro, 2004

Editor in Chief's Message: Saving power-Lessons from embedded systems.
IEEE Micro, 2004

EIC's Message: General-purpose versus application-specific processors.
IEEE Micro, 2004

EIC's Message: Chip-level microarchitecture trends.
IEEE Micro, 2004

Editor in Chief's Message: New Challenges and Burning Issues.
IEEE Micro, 2004

Understanding the energy efficiency of simultaneous multithreading.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Microarchitectural techniques for power gating of execution units.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

The Case for Lifetime Reliability-Aware Microprocessors.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

The Impact of Technology Scaling on Lifetime Reliability.
Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

2003
Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences.
IEEE Micro, 2003

Guest Editors' Introduction: Power and Complexity Aware Design.
IEEE Micro, 2003

Editor-in-Chief's Message: Adapting Old Paradigms to Meet New Challenges.
IEEE Micro, 2003

Design and Integration: Chip- and System-Level Challenges.
IEEE Micro, 2003

Issues and Trends in High-Performance Processor Cores.
IEEE Micro, 2003

Looking Forward to Bright New Beginnings.
IEEE Micro, 2003

New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors.
IBM J. Res. Dev., 2003

Dynamically Tuning Processor Resources with Adaptive Processing.
Computer, 2003

Energy Efficient Co-Adaptive Instruction Fetch and Issue.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Optimizing pipelines for power and performance.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Saving energy with just in time instruction delivery.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Tradeoffs in power-efficient issue queue design.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Synchronous Interlocked Pipelines.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
A circuit level implementation of an adaptive issue queue for power-aware microprocessors.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Ensuring Dependable Processor Performance: An Experience Report on Pre-Silicon Performance Validation.
Proceedings of the 2001 International Conference on Dependable Systems and Networks (DSN 2001) (formerly: FTCS), 2001

2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000

Testing for Function and Performance: Towards an Integrated Processor Validation Methodology.
J. Electron. Test., 2000

Simulation and analysis in the small: the case for simple models, metrics and microbenchmarks in computer architecture teaching and research.
Proceedings of the 2000 workshop on Computer architecture education, 2000

Performance and Functional Verification of Microprocessors.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

An Adaptive Issue Queue for Reduced Power at High Performance.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

1999
Challenges in processor modeling and validation [Guest Editors?? introduction].
IEEE Micro, 1999

Bounds modelling and compiler optimizations for superscalar performance tuning.
J. Syst. Archit., 1999

Performance Evaluation and Validation of Microprocessors.
Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1999

Validation of Turandot, a fast processor model for microarchitecture exploration.
Proceedings of the IEEE International Performance Computing and Communications Conference, 1999

1998
Performance Analysis and Its Impact on Design.
Computer, 1998

Performance Test Case Generation for Microprocessors.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997
Preface.
IBM J. Res. Dev., 1997

Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

1996
Computer architecture education in a corporate reengineering program.
Proceedings of the 1996 workshop on Computer architecture education, 1996

Representative Traces for Processor Models with Infinite Cache.
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

1995
Architectural timing verification of CMOS RISC processors.
IBM J. Res. Dev., 1995

1994
Architectural Performance Verification: PowerPC<sup>TM</sup> Processors.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Architectural Timing Verification and Test for Super Scalar Processors.
Proceedings of the Digest of Papers: FTCS/24, 1994

1993
MIPS-Driven Early Design and Analysis of VLSI CPU Chips.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1992
Workload-Driven Floorplanning for MIPS Optimization.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991
Early Performance Estimation of Super Scalar Machine Models.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
Synthesis of testable PLAs using adaptive heuristics for efficiency.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1988
A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem.
IEEE Trans. Computers, 1988

Interactive program improvement via EAVE: an expert adviser for vectorization.
Proceedings of the 2nd international conference on Supercomputing, 1988

Heuristic Rule-Based Program Transformations for Enhanced Vectorization.
Proceedings of the International Conference on Parallel Processing, 1988

Parallel logic/fault simulation of VLSI array logic.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Parallel Simulation and Test of VLSI Array Logic.
Proceedings of the VLSI Algorithms and Architectures, 3rd Aegean Workshop on Computing, 1988

1986
Optimal Code Generation for Expressions on Super Scalar Machines.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

1984
Design of Instruction Set Architectures for Support of High-Level Languages .
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

1982
Test generation for programmable logic arrays.
Proceedings of the 19th Design Automation Conference, 1982

Systematically derived instruction sets for high-level language support.
Proceedings of the 20th Annual Southeast Regional Conference, 1982


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