Alper Buyuktosunoglu

According to our database1, Alper Buyuktosunoglu authored at least 100 papers between 2000 and 2020.

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Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to adaptive micro-architectures and robust power management".

Timeline

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Bibliography

2020
Proactive power management in IBM z15.
IBM J. Res. Dev., 2020

STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.
CoRR, 2020


Data Compression Accelerator on IBM POWER9 and z15 Processors : Industrial Product.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Improving Efficiency in Large-Scale Decentralized Distributed Training.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Asymmetric Resilience: Exploiting Task-Level Idempotency for Transient Error Recovery in Accelerator-Based Systems.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems.
IEEE J. Solid State Circuits, 2019

Asymmetric Resilience for Accelerator-Rich Systems.
IEEE Comput. Archit. Lett., 2019

Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

A Highly Efficient Distributed Deep Learning System for Automatic Speech Recognition.
Proceedings of the Interspeech 2019, 2019

Resilient Low Voltage Accelerators for High Energy Efficiency.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Power Aware Heterogeneous Node Assembly.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
IBM POWER9 circuit design and energy optimization for 14-nm technology.
IBM J. Res. Dev., 2018

IBM z14 design methodology enhancements in the 14-nm technology node.
IBM J. Res. Dev., 2018

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Towards "Smarter" Vehicles Through Cloud-Backed Swarm Cognition.
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

Impact of Software Approximations on the Resiliency of a Video Summarization System.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2018

Energy-secure swarm power management.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Architectural Support for Cognitive Processing.
IEEE Micro, 2017

Machine learning techniques for taming the complexity of modern hardware design.
IBM J. Res. Dev., 2017

Mitigating Power Contention: A Scheduling Based Approach.
IEEE Comput. Archit. Lett., 2017

26.2 Power supply noise in a 22nm z13™ microprocessor.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Invited paper: Secure swarm intelligence: A new approach to many-core power management.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Invited paper: Resilient and energy-secure power management.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

libPRISM: an intelligent adaptation of prefetch and SMT levels.
Proceedings of the International Conference on Supercomputing, 2017

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017


BRAVO: Balanced Reliability-Aware Voltage Optimization.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Resilience characterization of a vision analytics application under varying degrees of approximation.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Characterization and mitigation of power contention across multiprogrammed workloads.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

2015
Robust power management in the IBM z13.
IBM J. Res. Dev., 2015

Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Power-efficient embedded processing with resilience and real-time constraints.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Resilient mobile cognition: Algorithms, innovations, and architectures.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Resilient, UAV-embedded real-time computing.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Increasing multicore system efficiency through intelligent bandwidth shifting.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
Adaptive Prefetching on POWER7: Improving Performance and Power Consumption.
ACM Trans. Parallel Comput., 2014

Special Series on Harsh Chips [Guest editors' introduction].
IEEE Micro, 2014

Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads.
IEEE Micro, 2014

Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Empirically derived abstractions in uncore power modeling for a server-class processor chip.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Characterization of transient error tolerance for a class of mobile embedded applications.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

3D stacking of high-performance processors.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Runtime Application Behavior Prediction Using a Statistical Metric Model.
IEEE Trans. Computers, 2013

SMT Malleability in IBM POWER5 and POWER6 Processors.
IEEE Trans. Computers, 2013

Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems.
IBM J. Res. Dev., 2013

SMT Switch: Software Mechanisms for Power Shifting.
IEEE Comput. Archit. Lett., 2013

Crank it up or dial it down: coordinated multiprocessor frequency and folding control.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

SMT-centric power-aware thread placement in chip multiprocessors.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
CPU Accounting for Multicore Processors.
IEEE Trans. Computers, 2012

Energy-Aware Computing.
IEEE Micro, 2012

Accurate Fine-Grained Processor Power Proxies.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Power management of multi-core chips: Challenges and pitfalls.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Making data prefetch smarter: adaptive prefetching on POWER7.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Energy-Aware Accounting and Billing in Large-Scale Computing Facilities.
IEEE Micro, 2011

Introducing the Adaptive Energy Management Features of the Power7 Chip.
IEEE Micro, 2011

Adaptive energy-management features of the IBM POWER7 chip.
IBM J. Res. Dev., 2011

Characterizing Power and Temperature Behavior of POWER6-Based System.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

A case for guarded power gating for multi-core processors.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Abstraction and microarchitecture scaling in early-stage power modeling.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
A Unified Prediction Method for Predicting Program Behavior.
IEEE Trans. Computers, 2010

Trends and techniques for energy efficient architectures.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Program behavior prediction using a statistical metric model.
Proceedings of the SIGMETRICS 2010, 2010

Guarded Power Gating in a Multi-core Setting.
Proceedings of the Computer Architecture, 2010

Runtime workload behavior prediction using statistical metric modeling with application to dynamic power management.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

Power-efficient, reliable microprocessor architectures: modeling and design methods.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Power and thermal characterization of POWER6 system.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
CPU Accounting in CMP Processors.
IEEE Comput. Archit. Lett., 2009

Dynamic power gating with quality guarantees.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs.
Proceedings of the PACT 2009, 2009

2008
Software-Controlled Priority Characterization of POWER5 Processor.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Exploring power management in multi-core systems.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Evaluating design tradeoffs in on-chip power management for CMPs.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Predicting Program Behavior Based On Objective Function Minimization.
Proceedings of the IEEE 10th International Symposium on Workload Characterization, 2007

Performance modeling for early analysis of multi-core systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

2005
Long-Term Workload Phases: Duration Predictions and Applications to DVFS.
IEEE Micro, 2005

A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004
Microarchitectural techniques for power gating of execution units.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
A Dynamically Tunable Memory Hierarchy.
IEEE Trans. Computers, 2003

Dynamically Tuning Processor Resources with Adaptive Processing.
Computer, 2003

Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Energy Efficient Co-Adaptive Instruction Fetch and Issue.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Tradeoffs in power-efficient issue queue design.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.
Proceedings of the SOC Design Methodologies, 2001

A circuit level implementation of an adaptive issue queue for power-aware microprocessors.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000

An Adaptive Issue Queue for Reduced Power at High Performance.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000


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