Joseph L. Ganley

Discret. Appl. Math., 2001

2000

A new heuristic for rectilinear Steiner trees.

[BibT_eX]

[DOI]

Ion I. Mandoiu

Vijay V. Vazirani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999

Provably good moat routing.

[BibT_eX]

[DOI]

Integr., 1999

Computing Optimal Rectilinear Steiner Trees: A Survey and Experimental Evaluation.

[BibT_eX]

[DOI]

Discret. Appl. Math., 1999

Efficient solution of systems of orientation constraints.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Physical Design, 1999

1998

Placement and Routing for Performance-Oriented FPGA Layout.

[BibT_eX]

[DOI]

VLSI Design, 1998

A Simple Approximation Algorithm for Two Problems in Circuit Design.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

The Power-p Steiner Tree Problem.

[BibT_eX]

Jeffrey S. Salowe

Nord. J. Comput., 1998

An Experimental Evaluation of Local Search Heuristics for Graph Partitioning.

[BibT_eX]

[DOI]

Computing, 1998

1997

Minimum-Congestion Hypergraph Embedding in a Cycle.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1997

Accuracy and fidelity of fast net length estimates.

[BibT_eX]

[DOI]

Integr., 1997

Improved Computation of Optimal Rectilinear Steiner Minimal Trees.

[BibT_eX]

[DOI]

Int. J. Comput. Geom. Appl., 1997

1996

Rectilinear Steiner trees on a checkerboard.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1996

Optimal and approximate bottleneck Steiner trees.

[BibT_eX]

[DOI]

Jeffrey S. Salowe

Oper. Res. Lett., 1996

A Provably Good Moat Routing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

Thumbnail rectilinear Steiner trees.

[BibT_eX]

[DOI]

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Performance-oriented placement and routing for field-programmable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

The Multi-Weighted Spanning Tree Problem (Extended Abstract).

[BibT_eX]

[DOI]

Mordecai J. Golin

Jeffrey S. Salowe

Proceedings of the Computing and Combinatorics, First Annual International Conference, 1995

1994

Heuristics for laying out information graphs.

[BibT_eX]

[DOI]

Computing, 1994

Optimal and Random Partitions of Random Graphs.

[BibT_eX]

[DOI]

Comput. J., 1994

Routing a Multi-Terminal Critical Net: Steiner Tree Construction in the Presence of Obstacles.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A faster dynamic programming algorithm for exact rectilinear Steiner minimal trees.

[BibT_eX]

[DOI]

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

An architecture-independent approach to FPGA routing based on multi-weighted graphs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

Optimal Rectilinear Steiner Minimal Trees in O (n<sup>2</sup>2.62<sup>n</sup>) Time.

[BibT_eX]