Joseph Riad

According to our database, Joseph Riad authored at least 7 papers between 2014 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A 175.2-mW 4-Stage OTA With Wide Load Range (400 pF-12 nF) Using Active Parallel Compensation.

Samuel Annor Fordjour, Joseph Riad, Edgar Sánchez-Sinencio

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Stabilizing Centralized Controller for On-Chip Power Delivery Networks.

Joseph Riad, Peng Li, Edgar Sánchez-Sinencio

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Power-Scaling Output-Compensated Three-Stage OTAs for Wide Load Range Applications.

Joseph Riad, Johan J. Estrada-López, Ivan R. Padilla-Cantoya, Edgar Sánchez-Sinencio

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Variation-Aware Heterogeneous Voltage Regulation for Multi-Core Systems-on-a-Chip with On-Chip Machine Learning.

Joseph Riad, Jianhao Chen, Edgar Sánchez-Sinencio, Peng Li

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Dynamic Heterogeneous Voltage Regulation for Systolic Array-Based DNN Accelerators.

Jianhao Chen, Joseph Riad, Edgar Sánchez-Sinencio, Peng Li

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2018

Design Space Exploration of Distributed On-Chip Voltage Regulation Under Stability Constraint.

Xin Zhan, Joseph Riad, Peng Li, Edgar Sánchez-Sinencio

IEEE Trans. Very Large Scale Integr. Syst., 2018

2014

Modeling and Simulation of a Pressure Sensing Solution Based on Silicon Carbide for Harsh Environment Applications.

Joseph Riad, Mourad N. El-Gamal, Hani F. Ragai

Proceedings of the UKSim-AMSS 16th International Conference on Computer Modelling and Simulation, 2014