Joshua Fazekas

According to our database, Joshua Fazekas authored at least 9 papers between 2004 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

An automated, FPGA-based reconfigurable, low-power RFID tag.

Alex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle

Microprocess. Microsystems, 2007

2006

Reducing power while increasing performance with supercisc.

Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster

ACM Trans. Embed. Comput. Syst., 2006

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power.

Alex K. Jones, Raymond R. Hoare, Dara Kusic, Justin Stander, Gayatri Mehta, Joshua Fazekas

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions.

Raymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster, Shen Chih Tung, Michael L. McCloud

EURASIP J. Adv. Signal Process., 2006

A Field Programmable RFID Tag and Associated Design Flow.

Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

An automated, reconfigurable, low-power RFID tag.

Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle

Proceedings of the 43rd Design Automation Conference, 2006

2005

Extracting Speedup From C-Code With Poor Instruction-Level Parallelism.

Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

An FPGA-based VLIW processor with custom hardware execution.

Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

A 64-way VLIW/SIMD FPGA architecture and design flow.

Alex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster, Sedric Boddie, Ahmed Muaydh

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004