Ivan S. Kourtev

According to our database1, Ivan S. Kourtev authored at least 22 papers between 1999 and 2009.

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Bibliography

2009
Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits.
Journal of Circuits, Systems, and Computers, 2009

2006
Delay Insertion Method in Clock Skew Scheduling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).
Microprocessors and Microsystems, 2006

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2004
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits.
IEEE Trans. VLSI Syst., 2004

Substrate coupling in digital circuits in mixed-signal smart-power systems.
IEEE Trans. VLSI Syst., 2004

Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Performance metrics for asynchronous digital circuits applicable to computer-aided design.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Performance improvement of edge-triggered sequential circuits.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Advanced timing of level-sensitive sequential circuits.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

LURU: global-scope FPGA technology mapping with content-addressable memories.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A 64-way VLIW/SIMD FPGA architecture and design flow.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Efficient CAD development for emerging technologies using Objective-C and Cocoa.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003
The Sandbox Design Experience Course.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Short Courses in System-on-a-Chip (SoC) Design.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Reduced dynamic swing domino logic.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling.
Journal of Circuits, Systems, and Computers, 2002

Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

1999
System Timing.
Proceedings of the VLSI Handbook., 1999

Clock skew scheduling for improved reliability via quadratic programming.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999


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