Alex K. Jones

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023

DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, September, 2023

Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT.

[BibT_eX]

[DOI]

IEEE Trans. Computers, April, 2023

Sustainable AI Processing at the Edge.

[BibT_eX]

[DOI]

IEEE Micro, 2023

REFRESH FPGAs: Sustainable FPGA Chiplet Architectures.

[BibT_eX]

[DOI]

CoRR, 2023

Parallel Driving for Fast Quantum Computing Under Speed Limits.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Realizing Extreme Endurance Through Fault-aware Wear Leveling and Improved Tolerance.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Co-Designed Architectures for Modular Superconducting Quantum Computers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022

Brain-inspired Cognition in Next-generation Racetrack Memories.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., November, 2022

Pinning Fault Mode Modeling for DWM Shifting.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge.

[BibT_eX]

[DOI]

IEEE Micro, 2022

Sustainable AI Processing at the Edge.

[BibT_eX]

[DOI]

CoRR, 2022

A Multi-domain Magneto Tunnel Junction for Racetrack Nanowire Strips.

[BibT_eX]

[DOI]

CoRR, 2022

FPIRM: Floating-point Processing in Racetrack Memories.

[BibT_eX]

[DOI]

CoRR, 2022

DNA Pre-Alignment Filter Using Processing Near Racetrack Memory.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2022

CORUSCANT: Fast Efficient Processing-in-Racetrack Memories.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Virtual Coset Coding for Encrypted Non-Volatile Memories with Multi-Level Cells.

[BibT_eX]

[DOI]

Stephen Longofono

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

H2H: heterogeneous model to heterogeneous system mapping with computation and communication awareness.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

A CASTLE With TOWERs for Reliable, Secure Phase-Change Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

XDWM: A 2D Domain Wall Memory.

[BibT_eX]

[DOI]

Arifa Hoque

Sanjukta Bhanja

CoRR, 2021

PIRM: Processing In Racetrack Memories.

[BibT_eX]

[DOI]

CoRR, 2021

Tuning Memory Fault Tolerance on the Edge.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Sustainable disturbance crosstalk mitigation in deeply scaled phase-change memory.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2020

Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond.

[BibT_eX]

[DOI]

CoRR, 2020

FLOWER and FaME: A Low Overhead Bit-Level Fault-map and Fault-Tolerance Approach for Deeply Scaled Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019

GreenChip: A tool for evaluating holistic sustainability of modern computing systems.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2019

Yielding optimized dependability assurance through bit inversion.

[BibT_eX]

[DOI]

Integr., 2019

PREMSim: A Resilience Framework for Modeling Traditional and Emerging Memory Reliability.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on Modeling, 2019

The Power of Orthogonality.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Toward Secure, Reliable, and Energy Efficient Phase-change Main Memory with MACE.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

Predicting Single Event Effects in DRAM.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018

Data Block Partitioning Methods to Mitigate Stuck-At Faults in Limited Endurance Memories.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Racetrack Queues for Extremely Low-Energy FIFOs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

RETROFIT: Fault-Aware Wear Leveling.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Counter Advance for Reliable Encryption in Phase Change Memory.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Mitigating Wordline Crosstalk Using Adaptive Trees of Counters.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Improving Sustainability Through Disturbance Crosstalk Mitigation in Deeply Scaled Phase-change Memory.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Achieving Secure, Reliable, and Sustainable Next Generation Computing Memories.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Dark Silicon Considered Harmful: A Case for Truly Green Computing.

[BibT_eX]

[DOI]

Erik Brunvand

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

2017

A Variable Length Coding Framework for Cost Function Reduction in Non-Volatile Memory Systems.

[BibT_eX]

[DOI]

CoRR, 2017

Counter-Based Tree Structure for Row Hammering Mitigation in DRAM.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

Mitigating bitline crosstalk noise in DRAM memories.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2017

Yoda: Judge Me by My Size, Do You?

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Dynamic partitioning to mitigate stuck-at faults in emerging memories.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Sustainable IC design and fabrication.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Sustainable fault management and error correction for next-generation main memories.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Holistic energy efficient crosstalk mitigation in DRAM.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Green Computing: New Challenges and Opportunities.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

ContextPreRF: Enhancing the Performance and Energy of GPUs With Nonuniform Register Access.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Weighted-Tuple: Fast and Accurate Synchronization for Parallel Architecture Simulators.

[BibT_eX]

[DOI]

Michael Moeng

IEEE Trans. Parallel Distributed Syst., 2016

FusedCache: A Naturally Inclusive, Racetrack Memory, Dual-Level Private Cache.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2016

Improving Bit Flip Reduction for Biased and Random Data.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Towards a commodity solution for the internet of things.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2016

Write Pulse Scaling for Energy Efficient STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Holistically evaluating the environmental impacts in modern computing systems.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

Modeling STT-RAM fabrication cost and impacts in NVSim.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

Leveraging ECC to Mitigate Read Disturbance, False Reads and Write Faults in STT-RAM.

[BibT_eX]

[DOI]

Rakan Maddah

Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2016

2015

Read Performance: The Newest Barrier in Scaled STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems.

[BibT_eX]

[DOI]

R. Iris Bahar

Yuan Xie

ACM Trans. Design Autom. Electr. Syst., 2015

A Roadmap and Plan of Action for Community-Supported Empirical Evaluation in Computer Architecture.

[BibT_eX]

[DOI]

Bruce R. Childers

Daniel Mossé

ACM SIGOPS Oper. Syst. Rev., 2015

Assessing interactions among multiple physiological systems during walking outside a laboratory: An Android based gait monitor.

[BibT_eX]

[DOI]

Comput. Methods Programs Biomed., 2015

Lynx: a self-organizing wireless sensor network with commodity palmtop computers.

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Reciprocal abstraction for computer architecture co-simulation.

[BibT_eX]

[DOI]

Michael Moeng

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Improving efficiency of wireless sensor networks through lightweight in-memory compression.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

MSCS: Multi-hop Segmented Circuit Switching.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

PRES: pseudo-random encoding scheme to increase the bit flip reduction in the memory.

[BibT_eX]

[DOI]

Rakan Maddah

Proceedings of the 52nd Annual Design Automation Conference, 2015

Domain-wall memory buffer for low-energy NoCs.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Multilane Racetrack caches: Improving efficiency through compression and independent shifting.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A Practical Data Classification Framework for Scalable and High Performance Chip-Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Weighted-Tuple Synchronization for Parallel Architecture Simulators.

[BibT_eX]

[DOI]

Michael Moeng

Proceedings of the IEEE 22nd International Symposium on Modelling, 2014

Design exploration of racetrack lower-level caches.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

EDA for extreme scale systems: design abstractions, metrics, and benchmarks.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Prefetching techniques for STT-RAM based last-level cache in CMP systems.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

<i>Ordering</i> circuit establishment in multiplane NoCs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

C1C: A configurable, compiler-guided STT-RAM L1 cache.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

PS-TLB: Leveraging page classification information for fast, scalable and efficient translation for future CMPs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

Implementation and validation of architectural space exploration techniques for domain-specific reconfigurable computing.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2013

"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Considering fabrication in sustainable computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Ocelot: A wireless sensor network and computing engine with commodity palmtop computers.

[BibT_eX]

[DOI]

Proceedings of the International Green Computing Conference, 2013

Green computing: A life cycle perspective.

[BibT_eX]

[DOI]

Proceedings of the International Green Computing Conference, 2013

Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Proactive circuit allocation in multiplane NoCs.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Compiler-Assisted Data Distribution and Network Configuration for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

Guest Editor's Note - Interaction between Compilers and Computer Architectures.

[BibT_eX]

[DOI]

Xin Yuan

J. Circuits Syst. Comput., 2012

Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2012

Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors.

[BibT_eX]

[DOI]

Yang Li

IEEE Comput. Archit. Lett., 2012

Déjà Vu Switching for Multiplane NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Cross-Layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access Characteristics.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A software approach for combating asymmetries of non-volatile memories.

[BibT_eX]

[DOI]

Yiran Chen

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Asymmetry of MTJ switching and its implication to STT-RAM designs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Practically private: enabling high performance CMPs through compiler-assisted data classification.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Two-hop Free-space based optical interconnects for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

Industrially inspired just-in-time (JIT) teaching.

[BibT_eX]

[DOI]

Steven P. Levitan

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

NoC-aware cache design for multithreaded execution on tiled chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2011

2010

An architectural space exploration tool for domain specific reconfigurable computing.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Automated modeling and emulation of interconnect designs for many-core chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Compiler-assisted data distribution for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

NoC-aware cache design for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

Guest Editors' Introduction to Security in Reconfigurable Systems Design.

[BibT_eX]

[DOI]

Patrick Schaumont

Steve Trimberger

ACM Trans. Reconfigurable Technol. Syst., 2009

Compiler Techniques for Efficient Communications in Circuit Switched Networks for Multiprocessor Systems.

[BibT_eX]

[DOI]

Shuyi Shao

IEEE Trans. Parallel Distributed Syst., 2009

Interconnect customization for a hardware fabric.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

A design automation and power estimation flow for RFID systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Non-Uniform "Fat-Meshes" for Chip Multiprocessors.

[BibT_eX]

[DOI]

Yu Zhang

Parallel Process. Lett., 2009

Winning with Pinning in NoC.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009

A low-power CMOS thyristor based delay element with programmability extensions.

[BibT_eX]

[DOI]

Gerold Joseph Dhanabalan

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Introduction to the special section on demonstrable software systems and hardware platforms II.

[BibT_eX]

[DOI]

Robert Walker

ACM Trans. Design Autom. Electr. Syst., 2008

Radio frequency identification prototyping.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Symbolic Expression Analysis for Compiled Communication.

[BibT_eX]

[DOI]

Parallel Process. Lett., 2008

Guest Editor's Note: Large-Scale Parallel Processing.

[BibT_eX]

[DOI]

Darren J. Kerbyson

Ramakrishnan Rajamony

Charles C. Weems

Parallel Process. Lett., 2008

A two-stage hardware scheduler combining greedy and optimal scheduling.

[BibT_eX]

[DOI]

Zhu Ding

J. Parallel Distributed Comput., 2008

A CAM-based intrusion detection system for single-packet attack detection.

[BibT_eX]

[DOI]

Ying Yu

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Physical layer design automation for RFID systems.

[BibT_eX]

[DOI]

Shen Chih Tung

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Reducing energy by exploring heterogeneity in a coarse-grain fabric.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007

An automated, FPGA-based reconfigurable, low-power RFID tag.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2007

Collaborative VLSI-CAD Instruction in the Digital Sandbox.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Exploring RFID Prototyping in the Virtual Laboratory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Interconnect Customization for a Coarse-grained Reconfigurable Fabric.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Linking Compilation and Visualization for Massively Parallel Programs.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions.

[BibT_eX]

[DOI]

Justin Stander

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006

Reducing power while increasing performance with supercisc.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2006

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

Passive active radio frequency identification tags.

[BibT_eX]

[DOI]

Int. J. Radio Freq. Identif. Technol. Appl., 2006

Entropy Based Evaluation of Communication Predictability in Parallel Applications.

[BibT_eX]

[DOI]

Jiang Zheng

Ahmed Amer

IEICE Trans. Inf. Syst., 2006

Speech Silicon: An FPGA Architecture for Real-Time Hidden Markov-Model-Based Speech Recognition.

[BibT_eX]

[DOI]

Jeffrey William Schuster

Kshitij Gupta

Raymond Hoare

EURASIP J. Embed. Syst., 2006

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2006

Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches.

[BibT_eX]

[DOI]

Zhu Ding

Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networks.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A compiler-based communication analysis approach for multiprocessor systems.

[BibT_eX]

[DOI]

Shuyi Shao

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Design space exploration for low-power reconfigurable fabrics.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

A Field Programmable RFID Tag and Associated Design Flow.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).

[BibT_eX]

[DOI]

Ivan S. Kourtev

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

An automated, reconfigurable, low-power RFID tag.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2005

High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2005

Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

On the Feasibility of Optical Circuit Switching for High Performance Computing Systems.

[BibT_eX]

[DOI]

Ramakrishnan Rajamony

Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

Extracting Speedup From C-Code With Poor Instruction-Level Parallelism.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

An FPGA-based VLIW processor with custom hardware execution.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Optimizing Technology Mapping for FPGAs Using CAMs.

[BibT_eX]

[DOI]

Joshua M. Lucas

Raymond Hoare

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004

Handling Data Streams while Compiling C Programs onto Hardware.

[BibT_eX]

[DOI]

Rajarshi Mukherjee

Prithviraj Banerjee

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

LURU: global-scope FPGA technology mapping with content-addressable memories.

[BibT_eX]

[DOI]

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A 64-way VLIW/SIMD FPGA architecture and design flow.

[BibT_eX]

[DOI]

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Efficient CAD development for emerging technologies using Objective-C and Cocoa.

[BibT_eX]

[DOI]

Bryan A. Brady

Ivan S. Kourtev

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003

An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs.

[BibT_eX]

[DOI]