Josip Mikulic

Orcid: 0000-0001-7079-668X

According to our database1, Josip Mikulic authored at least 25 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Analysis and compensation of stress effects on CMOS reference current sources.
Elektrotech. Informationstechnik, March, 2024

2023
Stress-Dependent MOSFET Model for Use in Circuit Simulations.
Proceedings of the 46th MIPRO ICT and Electronics Convention, 2023

Low-Power Frequency-Locked Loop Circuit with Static Frequency Offset Cancellation.
Proceedings of the 46th MIPRO ICT and Electronics Convention, 2023

Measurement System for Characterization of a Resistor Array in 180-nm CMOS Technology.
Proceedings of the 46th MIPRO ICT and Electronics Convention, 2023

2022
Low-Power Frequency-Locked Loop Circuit with Short Settling Time.
Proceedings of the 45th Jubilee International Convention on Information, 2022

Delay and Offset Compensated Relaxation Oscillator Core with Replica Integrator.
Proceedings of the 45th Jubilee International Convention on Information, 2022

2021
Post-Manufacturing Process and Temperature Calibration of a 2-MHz On-Chip Relaxation Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design and Testing of an 8-Bit Current DAC in 180-nm CMOS Technology.
Proceedings of the 44th International Convention on Information, 2021

200-MHz and 400-MHz Self-Biased Temperature-Compensated Ring Oscillators in 180-nm CMOS Technology.
Proceedings of the 44th International Convention on Information, 2021

Self-Referenced 32-kHz Rotating Capacitor Relaxation Oscillator with Chopped Comparator Offset-Voltage Cancellation.
Proceedings of the 44th International Convention on Information, 2021

2020
Programmable low-frequency divider in 180-nm CMOS technology.
Proceedings of the 43rd International Convention on Information, 2020

Design of CMOS Temperature Sensors Based on Ring Oscillators in 180-nm and 110-nm technology.
Proceedings of the 43rd International Convention on Information, 2020

Design of a tunable temperature coefficient voltage reference with low-dropout voltage regulator in 180-nm CMOS technology.
Proceedings of the 43rd International Convention on Information, 2020

Design and measurements of low power 32-kHz oscillators and a test interface in 180-nm CMOS technology.
Proceedings of the 43rd International Convention on Information, 2020

Semi-Analytical Estimation of On-Chip Intertwined Rectangular Transformer Parameters in 180 nm CMOS Technology.
Proceedings of the 43rd International Convention on Information, 2020

2019
A 1-MHz Relaxation Oscillator Core Employing a Self-Compensating Chopped Comparator Pair.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Design of Sense Amplifiers for Non-Volatile Memory.
Proceedings of the 42nd International Convention on Information and Communication Technology, 2019

Design Methodology of an On-Chip Inductor in 180 nm CMOS Technology.
Proceedings of the 42nd International Convention on Information and Communication Technology, 2019

2017
Temperature calibration of an on-chip relaxation oscillator.
Proceedings of the 40th International Convention on Information and Communication Technology, 2017

Characterization of measurement system for high-precision oscillator measurements.
Proceedings of the 40th International Convention on Information and Communication Technology, 2017

Fault-based test methodology for analog amplifier circuits.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

A 1-MHz on-chip relaxation oscillator with comparator delay cancelation.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
Key-Driver Analysis with Extended Back-Propagation Neural Network Based Importance-Performance Analysis (BPNN-IPA).
Proceedings of the Intelligent Decision Making in Quality Management, 2016

Relaxation oscillator calibration technique with comparator delay regulation.
Proceedings of the 39th International Convention on Information and Communication Technology, 2016

2012
Accounting for dynamics in attribute-importance and for competitor performance to enhance reliability of BPNN-based importance-performance analysis.
Expert Syst. Appl., 2012


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