Peter Sarson
Orcid: 0000-0002-7150-2281Affiliations:
- ams AG, Premstaetten, Austria
According to our database1,
Peter Sarson
authored at least 29 papers
between 2013 and 2019.
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Bibliography
2019
Adaptive Test for RF/Analog Circuit Using Higher Order Correlations among Measurements.
ACM Trans. Design Autom. Electr. Syst., 2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
2018
A Distortion Shaping Technique to Equalize Intermodulation Distortion Performance of Interpolating Arbitrary Waveform Generators in Automated Test Equipment.
J. Electron. Test., 2018
Measuring Group Delay of Frequency Downconverter Devices Using a Chirped RF Modulated Signal.
J. Electron. Test., 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
High efficient low cost EEPROM screening method in combination with an area optimized byte replacement strategy which enables high reliability EEPROMs.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Group delay measurement of frequency down-converter devices using chirped RF modulated signal.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
J. Electron. Test., 2017
An ATE Filter Characterization ToolKit Using a Discrete Chirped Excitation Signal as Stimulus.
J. Electron. Test., 2017
A technique for dynamic range improvement of intermodulation distortion products for an Interpolating DAC-based Arbitrary Waveform Generator using a phase switching algorithm.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the IEEE International Test Conference, 2017
A/MS benchmark circuits for comparing fault simulation, DFT, and test generation methods.
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
2016
Yield improvement of an EEPROM for automotive applications while maintaining high reliability.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Test time efficient group delay filter characterization technique using a discrete chirped excitation signal.
Proceedings of the 2016 IEEE International Test Conference, 2016
Variation and failure characterization through pattern classification of test data from multiple test stages.
Proceedings of the 2016 IEEE International Test Conference, 2016
Very low supply voltage room temperature test to screen low temperature soft blown fuse fails which result in a resistive bridge.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
2014
Proceedings of the 9th International Design and Test Symposium, 2014
2013
Proceedings of the 22nd Asian Test Symposium, 2013