Jubee Tada

According to our database1, Jubee Tada authored at least 21 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
An Implementation of an Instruction Controlled Cache Replacement Policy on a RISC-V Processor.
Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, 2023

2022
An Implementation of a Grid Square Codes Generator on a RISC-V Processor.
Int. J. Netw. Comput., 2022

An Implementation of a Pattern Matching Accelerator on a RISC-V Processor.
Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022

2021
An Implementation of a World Grid Square Codes Generator on a RISC-V Processor.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2020
A Cache Replacement Policy with Considering Fluctuation Patterns of Total Priority Value.
Int. J. Netw. Comput., 2020

2019
A Cache Replacement Policy with Considering Global Fluctuations of Priority Values.
Int. J. Netw. Comput., 2019

A Design Scheme for 3-D Stacked CNN Accelerators.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
An Adaptive Demotion Policy with Considering Temporal Locality.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017
An Adaptive Demotion Policy for High-Associativity Caches.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

2016
Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units.
SIGARCH Comput. Archit. News, 2016

A power-aware LLC control mechanism for the 3D-stacked memory system.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Design of a 3-D stacked floating-point Goldschmidt divider.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
An impact of circuit scale on the performance of 3-D stacked arithmetic units.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Performance evaluation of 3-D stacked 32-bit parallel multipliers.
SIGARCH Comput. Archit. News, 2013

Design of a 3-D stacked floating-point adder.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Vertically integrated processor and memory module design for vector supercomputers.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Poster: Exploring Design Space of a 3D Stacked Vector Cache - Designing a 3D Stacked Vector Cache using Conventional EDA Tools.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Abstract: Exploring Design Space of a 3D Stacked Vector Cache.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

2011
A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2009
Three-dimensional ultrasonic imaging operation using FPGA.
IEICE Electron. Express, 2009

Evaluation of fine grain 3-D integrated arithmetic units.
Proceedings of the IEEE International Conference on 3D System Integration, 2009


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