Hironori Nakajo

According to our database1, Hironori Nakajo authored at least 57 papers between 1994 and 2019.

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Bibliography

2019
Editor's Message to Special Issue on Embedded Systems Engineering.
JIP, 2019

Cow estrus detection with low-frequency accelerometer sensor by unsupervised learning.
Proceedings of the Tenth International Symposium on Information and Communication Technology, 2019

Parallelization of Recursive Function in Ruby-Based High-Level Synthesis.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Interactive Cultivation System for the Future IoT-Based Agriculture.
Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

2018
Fault-tolerant Routing based on Routing Capabilities in a Hyper-Star Graph.
J. Inf. Sci. Eng., 2018

Cow estrus detection via Discrete Wavelet Transformation and Unsupervised Clustering.
Proceedings of the Ninth International Symposium on Information and Communication Technology, 2018

A Deep Look into Logarithmic Quantization of Model Parameters in Neural Networks.
Proceedings of the 10th International Conference on Advances in Information Technology, 2018

Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices.
Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018

2017
Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Performance evaluation of an SoC for the real-time lens-free imager RALFIE.
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

2016
Design of real-time advanced lens free imager.
Proceedings of the Seventh Symposium on Information and Communication Technology, 2016

2011
Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis.
IEICE Transactions, 2011

A memory accelerator with gather functions for bandwidth-bound irregular applications.
Proceedings of the first workshop on Irregular applications: architectures and algorithm, 2011

Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Reconfigurable Android with an FPGA Accelerator for the Future Embedded Devices.
Proceedings of the Second International Conference on Networking and Computing, 2011

Detecting water waste activities for water-efficient living.
Proceedings of the UbiComp 2011: Ubiquitous Computing, 13th International Conference, 2011

2010
An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing.
The Journal of Supercomputing, 2010

Acceleration for MPI derived datatypes using an enhancer of memory and network.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Parallelizing Hilbert-Huang Transform on a GPU.
Proceedings of the First International Conference on Networking and Computing, 2010

An Effective Replacement Policy Focusing on Lifetime of a Cache Line.
Proceedings of the 2010 International Conference on Computer Design, 2010

2009
The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

Network Interface Architecture for Scalable Message Queue Processing.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

An Effective Replacement Strategy of Cache Memory for an SMT Processor.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor.
Proceedings of the 2009 International Conference on Computer Design, 2009

2008
Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 2008

An Enhancer of Memory and Network for Cluster and its Applications.
Proceedings of the Ninth International Conference on Parallel and Distributed Computing, 2008

Low-Complexity Bypass Network Using Small RAM.
Proceedings of the 2008 International Conference on Computer Design, 2008

2007
Introduction.
SIGARCH Computer Architecture News, 2007

Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

Performance evaluation on low-latency communication mechanism of DIMMnet-2.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

2006
A Model of Implementable SMT Processor on FPGA.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

Towards Reconfigurable Cache Memory for a Multithreaded Processor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

Implementation of PC Cluster System with Memory Mapped File by Commodity OS.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Development of a Thread Scheduler for SMT Processor Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.
Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

2004
Dynamic Allocation of Physical Register Banks for an SMT Processor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

A New Memory Module for Memory Intensive Applications.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

2003
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Implementation and Evaluation of a Thread Library for Multithreaded Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

2002
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot.
Cluster Computing, 2002

Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot.
Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

2000
A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links.
International Journal of Parallel Programming, 2000

Coherence Protocol for Home Proxy Cache on RHiNET.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000

MEMOnet : Network interface plugged into a memory slot.
Proceedings of the 2000 IEEE International Conference on Cluster Computing (CLUSTER 2000), November 28th, 2000

1998
Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface.
Proceedings of the High-Performance Computing and Networking, 1998

1997
An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links.
Proceedings of the High Performance Computing, International Symposium, 1997

An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1.
Proceedings of the 11th international conference on Supercomputing, 1997

1996
A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1.
Proceedings of the 16th International Conference on Distributed Computing Systems, 1996

1995
High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

1994
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations.
Proceedings of the International Symposium on Parallel Architectures, 1994


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