Hironori Nakajo

According to our database, Hironori Nakajo authored at least 61 papers between 1994 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Learning Algorithm for LesserDNN, a DNN with Quantized Weights.

Masashi Takemoto, Yasutake Masuda, Jingyong Cai, Hironori Nakajo

Proceedings of the 12th International Symposium on Information and Communication Technology, 2023

2022

Implementation of a RISC-V SMT Core in an AI processor.

Hidetaro Tanaka, Tomoaki Tanaka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo

Proceedings of the 11th International Symposium on Information and Communication Technology, 2022

2020

Editor's Message to Special Issue on Embedded Systems Engineering.

Hironori Nakajo

J. Inf. Process., 2020

A Ruby-Based Hardware/Software Co-Design Environment with Functional Reactive Programming: Mulvery.

Daichi Teruya, Hironori Nakajo

IEICE Trans. Inf. Syst., 2020

2019

Cow estrus detection with low-frequency accelerometer sensor by unsupervised learning.

Tran Viet Toan, Rin Nishikawa, Le Tien Thanh, Masashi Takemoto, Tran Van Hoai, Huynh Thi Thanh Binh, Hironori Nakajo

Proceedings of the Tenth International Symposium on Information and Communication Technology, 2019

Parallelization of Recursive Function in Ruby-Based High-Level Synthesis.

Ryota Yamashita, Daichi Teruya, Hironori Nakajo

Proceedings of the International Conference on Field-Programmable Technology, 2019

Interactive Cultivation System for the Future IoT-Based Agriculture.

Kesevan Veloo, Hayate Kojima, Shogo Takata, Masashi Nakamura, Hironori Nakajo

Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

2018

Fault-tolerant Routing based on Routing Capabilities in a Hyper-Star Graph.

Yo Nishiyama, Yuko Sasaki, Yuki Hirai, Hironori Nakajo, Keiichi Kaneko

J. Inf. Sci. Eng., 2018

Cow estrus detection via Discrete Wavelet Transformation and Unsupervised Clustering.

Le Tien Thanh, Rin Nishikawa, Masashi Takemoto, Huynh Thi Thanh Binh, Hironori Nakajo

Proceedings of the Ninth International Symposium on Information and Communication Technology, 2018

Operation in Partitioned Circuits with Scalable Hardware Mechanism.

Yusuke Katoh, Hironari Yoshiuchi, Yoshio Murata, Hironori Nakajo

Proceedings of the 15th International Joint Conference on Computer Science and Software Engineering, 2018

A Deep Look into Logarithmic Quantization of Model Parameters in Neural Networks.

Jingyong Cai, Masashi Takemoto, Hironori Nakajo

Proceedings of the 10th International Conference on Advances in Information Technology, 2018

Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices.

Jingyong Cai, Masashi Takemoto, Hironori Nakajo

Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018

2017

Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool.

Yuto Ishikawa, Keitaro Yanai, Keisuke Koike, Takefumi Miyoshi, Hironori Nakajo

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Performance evaluation of an SoC for the real-time lens-free imager RALFIE.

Masashi Takemoto, Ryota Suzuki, Katsuhiko Umeno, Masayuki Yashiro, Tetsuya Ryuchi, Kohta Ohshima, Naoya Kitagawa, Hironori Nakajo

Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

2016

Design of real-time advanced lens free imager.

Masashi Takemoto, Ryota Suzuki, Katsuhiko Umeno, Masayuki Yashiro, Tetsuya Ryuchi, Kohta Ohshima, Naoya Kitagawa, Hironori Nakajo

Proceedings of the Seventh Symposium on Information and Communication Technology, 2016

2011

Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis.

Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo

IEICE Trans. Inf. Syst., 2011

A memory accelerator with gather functions for bandwidth-bound irregular applications.

Noboru Tanabe, Boonyasitpichai Nuttapon, Hironori Nakajo, Yuka Ogawa, Junko Kogou, Masami Takata, Kazuki Joe

Proceedings of the first workshop on Irregular applications: architectures and algorithm, 2011

Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage.

Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning

Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Reconfigurable Android with an FPGA Accelerator for the Future Embedded Devices.

Hironori Nakajo, Keisuke Koike, Atsushi Ohta, Kohta Ohshima, Kaori Fujinami

Proceedings of the Second International Conference on Networking and Computing, 2011

Detecting water waste activities for water-efficient living.

Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning

Proceedings of the UbiComp 2011: Ubiquitous Computing, 13th International Conference, 2011

2010

An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing.

Noboru Tanabe, Hirotaka Hakozaki, Hiroshi Ando, Yasunori Dohi, Zhengzhe Luo, Hironori Nakajo

J. Supercomput., 2010

Acceleration for MPI derived datatypes using an enhancer of memory and network.

Noboru Tanabe, Hironori Nakajo

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Parallelizing Hilbert-Huang Transform on a GPU.

Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo

Proceedings of the First International Conference on Networking and Computing, 2010

An Effective Replacement Policy Focusing on Lifetime of a Cache Line.

Hiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo

Proceedings of the 2010 International Conference on Computer Design, 2010

2009

The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing.

Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

Network Interface Architecture for Scalable Message Queue Processing.

Noboru Tanabe, Atsushi Ohta, Pulung Waskito, Hironori Nakajo

Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

An Effective Replacement Strategy of Cache Memory for an SMT Processor.

Yoshiyasu Ogasawara, Hironori Nakajo

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor.

Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo

Proceedings of the 2009 International Conference on Computer Design, 2009

2008

Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network.

Noboru Tanabe, Hironori Nakajo

Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 2008

An Enhancer of Memory and Network for Cluster and its Applications.

Noboru Tanabe, Hironori Nakajo

Proceedings of the Ninth International Conference on Parallel and Distributed Computing, 2008

Low-Complexity Bypass Network Using Small RAM.

Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita

Proceedings of the 2008 International Conference on Computer Design, 2008

2007

Introduction.

Kenji Kise, Toshinori Sato, Hironori Nakajo

SIGARCH Comput. Archit. News, 2007

Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices.

Satoshi Watanabe, Yoshiyasu Ogasawara, Ippei Tate, Hirofumi Yano, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.

Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

Performance evaluation on low-latency communication mechanism of DIMMnet-2.

Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

2006

A Model of Implementable SMT Processor on FPGA.

Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

Towards Reconfigurable Cache Memory for a Multithreaded Processor.

Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

Implementation of PC Cluster System with Memory Mapped File by Commodity OS.

Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot.

Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

Development of a Thread Scheduler for SMT Processor Architecture.

Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.

Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.

Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.

Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo

Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2.

Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

2004

Dynamic Allocation of Physical Register Banks for an SMT Processor.

Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

A New Memory Module for Memory Intensive Applications.

Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

2003

A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture.

Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Implementation and Evaluation of a Thread Library for Multithreaded Architecture.

Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.

Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

2002

Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot.

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano

Clust. Comput., 2002

Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot.

Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano

Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

2000

A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links.

Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda

Int. J. Parallel Program., 2000

Coherence Protocol for Home Proxy Cache on RHiNET.

Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano

Proceedings of the 5th International Symposium on Parallel Architectures, 2000

MEMOnet : Network interface plugged into a memory slot.

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano

Proceedings of the 2000 IEEE International Conference on Cluster Computing (CLUSTER 2000), November 28th, 2000

1998

Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface.

Hironori Nakajo, Hidekazu Tanaka, Yoshinori Nakanishi, Masaki Kohata, Yukio Kaneda

Proceedings of the High-Performance Computing and Networking, 1998

1997

An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links.

Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda

Proceedings of the High Performance Computing, International Symposium, 1997

An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1.

Hironori Nakajo, Satoshi Ohtani, Takashi Matsumoto, Masadi Kohata, Kei Hiraki, Yukio Kaneda

Proceedings of the 11th international conference on Supercomputing, 1997

1996

A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1.

Hironori Nakajo, Satoshi Ohtani, Yukio Kaneda

Proceedings of the 16th International Conference on Distributed Computing Systems, 1996

1995

High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1.

Hironori Nakajo, Takashi Matsumoto, Masaki Kohata, Hideo Matsuda, Kei Hiraki, Yukio Kaneda

Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

1994

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations.

Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori

Proceedings of the International Symposium on Parallel Architectures, 1994