Hiroyuki Takizawa

According to our database1, Hiroyuki Takizawa authored at least 96 papers between 1999 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
A Machine Learning-Based Approach for Selecting SpMV Kernels and Matrix Storage Formats.
IEICE Transactions, 2018

Use of Code Structural Features for Machine Learning to Predict Effective Optimizations.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Preconditioner Auto-Tuning Using Deep Learning for Sparse Iterative Algorithms.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

Investigating the Effects of Dynamic Thread Team Size Adjustment for Irregular Applications.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

A Failure Prediction-Based Adaptive Checkpointing Method with Less Reliance on Temperature Monitoring for HPC Applications.
Proceedings of the IEEE International Conference on Cluster Computing, 2018

Automatic Hyperparameter Tuning of Machine Learning Models under Time Constraints.
Proceedings of the IEEE International Conference on Big Data, 2018

Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Potential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE.
The Journal of Supercomputing, 2017

Toward Dynamic Load Balancing across OpenMP Thread Teams for Irregular Workloads.
IJNC, 2017

A Directive Generation Approach to High Code-Maintainability for Various HPC Systems.
IJNC, 2017

Energy-Performance Modeling of Speculative Checkpointing for Exascale Systems.
IEICE Transactions, 2017

Optimizing Energy Consumption on HPC Systems with a Multi-Level Checkpointing Mechanism.
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

A Customizable Auto-Tuning Scenario with User-Defined Code Transformations.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

An Application-Level Incremental Checkpointing Mechanism with Automatic Parameter Tuning.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Designing an Open Database of System-Aware Code Optimizations.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

A Memory Congestion-Aware MPI Process Placement for Modern NUMA Systems.
Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017

Vectorization-Aware Loop Optimization with User-Defined Code Transformations.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

Performance and Power Analysis of SX-ACE Using HP-X Benchmark Programs.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016
Translation of Large-Scale Simulation Codes for an OpenACC Platform Using the Xevolver Framework.
IJNC, 2016

A Code Selection Mechanism Using Deep Learning.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

The Importance of Dynamic Load Balancing among OpenMP Thread Teams for Irregular Workloads.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Xevdriver: A Software System Supporting XML-based Source-to-Source Code Transformations on Fortran Programs.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

A Directive Generation Approach Using User-Defined Rules.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

A User-Defined Code Transformation Approach to Overlapping MPI Communication with Computation.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

A cache partitioning mechanism to protect shared data for CMPs.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

2015
Optimized Data Transfers Based on the OpenCL Event Management Mechanism.
Scientific Programming, 2015

Identification and Elimination of Platform-Specific Code Smells in High Performance Computing Applications.
IJNC, 2015

FLEXII: A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms.
IEICE Transactions, 2015

A Light-Weight Rollback Mechanism for Testing Kernel Variants in Auto-Tuning.
IEICE Transactions, 2015

A Case Study of User-Defined Code Transformations for Data Layout Optimizations.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Xevtgen: Fortran Code Transformer Generator for High Performance Scientific Codes.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Migration of an Atmospheric Simulation Code to an OpenACC Platform Using the Xevolver Framework.
Proceedings of the Third International Symposium on Computing and Networking, 2015

A Verification Framework for Streamlining Empirical Auto-Tuning.
Proceedings of the Third International Symposium on Computing and Networking, 2015

An energy-efficient dynamic memory address mapping mechanism.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

2014
MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications.
IEICE Transactions, 2014

Automatic Parameter Tuning of Hierarchical Incremental Checkpointing.
Proceedings of the High Performance Computing for Computational Science - VECPAR 2014 - 11th International Conference, Eugene, OR, USA, June 30, 2014

A Compiler-Assisted OpenMP Migration Method Based on Automatic Parallelizing Information.
Proceedings of the Supercomputing - 29th International Conference, 2014

An Approach to Customization of Compiler Directives for Application-Specific Code Transformations.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

A Platform-Specific Code Smell Alert System for High Performance Computing Applications.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Xevolver: An XML-based code translation framework for supporting HPC application migration.
Proceedings of the 21st International Conference on High Performance Computing, 2014

An energy optimization method for vector processing mechanisms.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

On-chip checkpointing with 3D-stacked memories.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts.
IEICE Transactions, 2013

Balanced Ternary Quantum Voltage Generator Based on Zero Crossing Shapiro Steps in Asymmetric Two-Junction SQUIDs.
IEICE Transactions, 2013

clMPI: An OpenCL Extension for Interoperation with the Message Passing Interface.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Design and evaluation of a media-oriented vector processor with a multi-banked cache memory.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

A flexible insertion policy for dynamic cache resizing mechanisms.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

2012
Poster: Exploring Design Space of a 3D Stacked Vector Cache - Designing a 3D Stacked Vector Cache using Conventional EDA Tools.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Abstract: Exploring Design Space of a 3D Stacked Vector Cache.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

GPU implementation of phase-based stereo correspondence and its application.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

A media-oriented vector architectural extension with a high bandwidth cache system.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012

A capacity-efficient insertion policy for dynamic cache resizing mechanisms.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

An out-of-order vector processing mechanism for multimedia applications.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011
Power-Aware Dynamic Cache Partitioning for CMPs.
Trans. HiPEAC, 2011

A Self-Organized Overlay Network Management Mechanism for Heterogeneous Environments.
JIP, 2011

A Network Clustering Algorithm for Sybil-Attack Resisting.
IEICE Transactions, 2011

A History-Based Performance Prediction Model with Profile Data Classification for Automatic Task Allocation in Heterogeneous Computing Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011

CheCL: Transparent Checkpointing and Process Migration of OpenCL Applications.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

NVCR: A Transparent Checkpoint-Restart Library for NVIDIA CUDA.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Effects of 3-D stacked vector cache on energy consumption.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Resisting Sybil Attack By Social Network and Network Clustering.
Proceedings of the Tenth Annual International Symposium on Applications and the Internet, 2010

A voting-based working set assessment scheme for dynamic cache resizing mechanisms.
Proceedings of the 28th International Conference on Computer Design, 2010

A Majority-Based Control Scheme for Way-Adaptable Caches.
Proceedings of the Facing the Multicore-Challenge, 2010

A Load-Forwarding Mechanism for the Vector Architecture in Multimedia Applications.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Cache partitioning strategies for 3-D stacked vector processors.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Design and early evaluation of a 3-D die stacked chip multi-vector processor.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Automatic Tuning of CUDA Execution Parameters for Stencil Processing.
Proceedings of the Software Automatic Tuning, From Concepts to State-of-the-Art Results, 2010

2009
Evaluating Computational Performance of Backpropagation Learning on Graphics Hardware.
Electr. Notes Theor. Comput. Sci., 2009

Performance evaluation of NEC SX-9 using real science and engineering applications.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

CheCUDA: A Checkpoint/Restart Tool for CUDA Applications.
Proceedings of the 2009 International Conference on Parallel and Distributed Computing, 2009

3D on-chip memory for the vector architecture.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
A Reliability Model for Result Checking in Volunteer Computing.
Proceedings of the 2008 International Symposium on Applications and the Internet, 2008

Consideration of Resource Access History for Optimizing Overlay Networks in P2P-Based Resource Discovery.
Proceedings of the 2008 International Symposium on Applications and the Internet, 2008

A Utility-Based Double Auction Mechanism for Efficient Grid Resource Allocation.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Implementation and evaluation of a distributed and cooperative load-balancing mechanism for dependable volunteer computing.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

SPRAT: Runtime processor selection for energy-aware computing.
Proceedings of the 2008 IEEE International Conference on Cluster Computing, 29 September, 2008

A Performance Study of Secure Data Mining on the Cell Processor.
Proceedings of the 8th IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2008), 2008

2007
Partial distortion entropy maximization for online data clustering.
Neural Networks, 2007

A dependable Peer-to-Peer computing platform.
Future Generation Comp. Syst., 2007

2006
Hierarchical parallel processing of large scale data clustering on a PC cluster with GPU co-processing.
The Journal of Supercomputing, 2006

A distributed and cooperative load balancing mechanism for large-scale P2P systems.
Proceedings of the 2006 International Symposium on Applications and the Internet Workshops (SAINT 2006 Workshops), 2006

Design and Implementation of an Efficient Search Mechanism Based on the Hybrid P2P Model for Ubiquitous Computing Systems.
Proceedings of the 2006 International Symposium on Applications and the Internet (SAINT 2006), 2006

Implications of Memory Performance for Highly Efficient Supercomputing of Scientific Applications.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

Radiative Heat Transfer Simulation Using Programmable Graphics Hardware.
Proceedings of the 5th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2006) and 1st IEEE/ACIS International Workshop on Component-Based Software Engineering, 2006

2005
Locality analysis to control dynamically way-adaptable caches.
SIGARCH Computer Architecture News, 2005

A Self-Organizing Overlay Network to Exploit the Locality of Interests for Effective Resource Discovery in P2P Systems.
Proceedings of the 2005 IEEE/IPSJ International Symposium on Applications and the Internet (SAINT 2005), 31 January, 2005

A Workflow Management Mechanism for Peer-to-Peer Computing Platforms.
Proceedings of the Parallel and Distributed Processing and Applications, 2005

An Incremental Photon-Mapping Algorithm for Fast Walk-Through Animations.
Proceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, 2005

2004
Efficient parallel processing of competitive learning algorithms.
Parallel Computing, 2004

A Fast Computation Scheme of Partial Distortion Entropy Updating.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Multi-grain Parallel Processing of Data-Clustering on Programmable Graphics Hardware.
Proceedings of the Parallel and Distributed Processing and Applications, 2004

2003
A Comparison Study of Vector Quantization Codebook Design Algorithms based on the Equidistortion Principle.
Proceedings of the 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), 2003

A Decision Criterion to Relocate Codewords for Adaptive Vector Quantization.
Proceedings of the 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), 2003

2002
Parallel Algorithm for the Law-of-the-Jungle Learning to the Fast Design of Optimal Codebooks.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

1999
A self-organizing network system forming memory from nonstationary probability distributions.
Proceedings of the International Joint Conference Neural Networks, 1999


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