Jun Sakamaki

Orcid: 0009-0006-5666-5484

According to our database1, Jun Sakamaki authored at least 8 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset.
IEEE J. Solid State Circuits, April, 2025

A LEO Satellite Mounted 256-Element 19 GHz CMOS Phased-Array Transmitter With On-Chip Amplitude and Phase Monitor.
IEEE Access, 2025

A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023
A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations.
IEEE J. Solid State Circuits, December, 2023

A 37-43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD.
IEEE J. Solid State Circuits, October, 2023

A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023


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