Jung Pill Kim

According to our database¹, Jung Pill Kim authored at least 25 papers between 2003 and 2019.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2019

Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017

A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Realizing Transparent OS/Apps Compression in Mobile Devices at Zero Latency Overhead.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

2016

An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Equalization scheme analysis for high-density spin transfer torque random access memory.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

Area-optimal sensing circuit designs in deep submicrometer STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Reference-circuit analysis for high-bandwidth spin transfer torque random access memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Split-Path Sensing Circuit for Spin Torque Transfer MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

An MTJ-based non-volatile flip-flop for high-performance SoC.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2014

High-performance low-power magnetic tunnel junction based non-volatile flip-flop.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

2011

MTJ based non-volatile flip-flop in deep submicron technology.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

2003

A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme.

[BibT_eX]

[DOI]

Jung Pill Kim

Woodward Yang

Han-Yuan Tan

IEEE J. Solid State Circuits, 2003

Jung Pill Kim

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...