Seong-Ook Jung

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization.

[BibT_eX]

[DOI]

Giseok Kim

Jaehyun Park

Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023

An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, November, 2023

An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

High-Precision and Low-Power Offset Canceling Tri-State Sensing Latch in NAND Flash Memory.

[BibT_eX]

[DOI]

Taeyun Lee

In Jun Jung

IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2023

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2023

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

SIF-NPU: A 28nm 3.48 TOPS/W 0.25 TOPS/mm2 CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-Resolution.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021

Adaptive Sensing Voltage Modulation Technique in Cross-Point OTS-PRAM.

[BibT_eX]

[DOI]

Kwang Woo Lee

IEEE Trans. Very Large Scale Integr. Syst., 2021

Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell With Auto Write-Back Technique.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

STT-MRAM Sensing: A Review.

[BibT_eX]

[DOI]

Taehui Na

Seung-Hyuk Kang

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface With VOH Drift Control.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 6.9-μm2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM.

[BibT_eX]

[DOI]

Suk Min Kim

Byungkyu Song

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation.

[BibT_eX]

[DOI]

IEEE Access, 2021

Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells.

[BibT_eX]

[DOI]

IEEE Access, 2021

High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops.

[BibT_eX]

[DOI]

IEEE Access, 2021

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM.

[BibT_eX]

[DOI]

Ki-Ryong Kim

IEEE Access, 2021

All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash.

[BibT_eX]

[DOI]

IEEE Access, 2021

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling.

[BibT_eX]

[DOI]

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Intrinsic Capacitance based Multi bit Computing in Memory.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

CNN encryption using XOR Gate for Hardware Optimization.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

2020

pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation.

[BibT_eX]

[DOI]

Juhyun Park

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM.

[BibT_eX]

[DOI]

Hong Keun Ahn

IEEE Trans. Very Large Scale Integr. Syst., 2020

Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability.

[BibT_eX]

[DOI]

Sehee Lim

Byungkyu Song

IEEE Trans. Inf. Forensics Secur., 2020

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Current Measurement Transducer Based on Current-To-Voltage-To-Frequency Converting Ring Oscillator with Cascade Bias Circuit.

[BibT_eX]

[DOI]

Jongha Park

Jung-Hyun Park

Sensors, 2020

CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution.

[BibT_eX]

[DOI]

IEEE Access, 2020

Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC.

[BibT_eX]

[DOI]

IEEE Access, 2020

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache.

[BibT_eX]

[DOI]

IEEE Access, 2020

A Read Voltage Modulation Technique for Leakage Current Compensation in Cross-Point OTS-PRAM.

[BibT_eX]

[DOI]

Kwang Woo Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM.

[BibT_eX]

[DOI]

Suk Min Kim

Byungkyu Song

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

2018

All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

0.293-mm2 Fast Transient Response Hysteretic Quasi-V2 DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-µm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM.

[BibT_eX]

[DOI]

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Triplet-based Spike Timing Dependent Plasticity Circuit Design for three-terminal Spintronic Synapse.

[BibT_eX]

[DOI]

Beomsang Yoo

Ki-Ryong Kim

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Power-Gated 9T SRAM Cell for Low-Energy Operation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

GRO-TDC with gate-switch-based delay cell halving resolution limit.

[BibT_eX]

[DOI]

Jung-Hyun Park

Int. J. Circuit Theory Appl., 2017

2016

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm.

[BibT_eX]

[DOI]

Ki-Ryong Kim

IEICE Electron. Express, 2016

Equalization scheme analysis for high-density spin transfer torque random access memory.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Area-optimal sensing circuit designs in deep submicrometer STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Low power SRAM design for 14 nm GAA Si-nanowire technology.

[BibT_eX]

[DOI]

Microelectron. J., 2015

Reference-circuit analysis for high-bandwidth spin transfer torque random access memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

Comparative Study of Various Latch-Type Sense Amplifiers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Split-Path Sensing Circuit for Spin Torque Transfer MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

An MTJ-based non-volatile flip-flop for high-performance SoC.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2014

High-performance low-power magnetic tunnel junction based non-volatile flip-flop.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Pseudo NMOS based sense amplifier for high speed single-ended SRAM.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

ADDLL for Clock-Deskew Buffer in High-Performance SoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Dynamic mixed serial-parallel content addressable memory (DMSP CAM).

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2013

A comparative study of STT-MTJ based non-volatile flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 0.67nJ/S time-domain temperature sensor for low power on-chip thermal management.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2013

All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2013, 2013

All-digital 90° phase-shift DLL with a dithering jitter suppression scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM).

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Integration of dual channel timing formatter system for high speed memory test equipment.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction.

[BibT_eX]

[DOI]

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

Sensing margin trend with technology scaling in MRAM.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2011

MTJ based non-volatile flip-flop in deep submicron technology.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

2010

A DLL based clock generator for low-power mobile SoCs.

[BibT_eX]

[DOI]

Dong Hun Jung

IEEE Trans. Consumer Electron., 2010

A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2010

Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2010

Process variation tolerant all-digital multiphase DLL for DDR3 interface.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation.

[BibT_eX]

[DOI]

Myeong-Eun Hwang

Kaushik Roy

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Serial-Parallel Content Addressable Memory with a Conditional Driver (SPCwCD).

[BibT_eX]

[DOI]

Mingu Kang

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory.

[BibT_eX]

[DOI]

Sei-Seung Yoon

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.

[BibT_eX]

[DOI]

Myeong-Eun Hwang

Kaushik Roy

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006

Thyristor-Based Volatile Memory in Nano-Scale CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 32-bit carry lookahead adder using dual-path all-N logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

2004

A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Noise-aware interconnect power optimization in domino logic synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Minimum delay optimization for domino circuits - a coupling-aware approach.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

Timing constraints for domino logic gates with timing-dependent keepers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002

Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology

[BibT_eX]

[DOI]

PhD thesis, 2002

Noise constrained transistor sizing and power optimization for dual Vst domino logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Optimal Timing for Skew-Tolerant High-Speed Domino Logic.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Low-swing clock domino logic incorporating dual supply and dual threshold voltages.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

New current-mode sense amplifiers for high density DRAM and PIM architectures.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT.

[BibT_eX]

[DOI]

Seung-Moon Yoo

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Coupling-aware minimum delay optimization for domino logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Skew-tolerant high-speed (STHS) domino logic.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Noise constrained power optimization for dual VT domino logic.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test.

[BibT_eX]

[DOI]

Seung-Moon Yoo

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Transistor sizing for reliable domino logic design in dual threshold voltage technologies.

[BibT_eX]

[DOI]