Sara Choi

Orcid: 0000-0002-4179-7680

According to our database¹, Sara Choi authored at least 8 papers between 2016 and 2022.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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Bibliography

2022

A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC.

[BibT_eX]

[DOI]

IEEE Access, 2020

2019

Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2016

Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Area-optimal sensing circuit designs in deep submicrometer STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Sara Choi

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