Junghyun Yoon

Orcid: 0009-0000-2775-9103

According to our database1, Junghyun Yoon authored at least 9 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A Continuous-Time Zoom ADC With Coarse Noise-Shaping ADC and Interstage Low-Pass Filter.
IEEE J. Solid State Circuits, April, 2026

Breaking Standard Cell Margin Constraints for Area-Efficient VLSI Design.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

SMT-Based Optimal Transistor Folding and Placement for Standard Cell Layout Generation.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

Standard Cell Layout Generation: Methodological Evolution and Architectural Impacts.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
A 500-kS/s Continuous-Time Linear-Exponential Incremental ADC Achieving 90.1-dB DR and 103.1-dB SFDR.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2025

An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth.
IEEE J. Solid State Circuits, February, 2025

Mitigating Routability Problems in Complementary-FET-based VLSI Designs.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024
Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
A 243μW 97.4dB-DR 50kHz-BW Multi-Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023


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