Heechun Park
Orcid: 0000-0003-2796-518X
According to our database1,
Heechun Park
authored at least 28 papers
between 2013 and 2024.
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Bibliography
2024
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024
Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024
Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., May, 2023
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
ACM J. Emerg. Technol. Comput. Syst., 2022
Speeding-up neuromorphic computation for neural networks: Structure optimization approach.
Integr., 2022
Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2021
ACM Trans. Design Autom. Electr. Syst., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis.
Proceedings of the 18th International SoC Design Conference, 2021
2020
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020
2019
Integr., 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Structure optimizations of neuromorphic computing architectures for deep neural network.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
2013
Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013