Heechun Park

According to our database, Heechun Park authored at least 24 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration.

Sojung Park, Heechun Park

Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023

Eliminating Minimum Implant Area Violations With Design Quality Preservation.

Eunsol Jeong, Taewhan Kim, Heechun Park

IEEE Trans. Very Large Scale Integr. Syst., May, 2023

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.

Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs.

Arjun Chaudhuri, Sanmitra Banerjee, Jinwoo Kim, Heechun Park, Bon Woong Ku, Sukeshwar Kannan, Krishnendu Chakrabarty, Sung Kyu Lim

ACM J. Emerg. Technol. Comput. Syst., 2022

Speeding-up neuromorphic computation for neural networks: Structure optimization approach.

Heechun Park, Taewhan Kim

Integr., 2022

Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs.

Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

A Systematic Removal of Minimum Implant Area Violations under Timing Constraint.

Eunsol Jeong, Heechun Park, Taewhan Kim

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems.

Gauthaman Murali, Heechun Park, Eric Qin, Hakki Mert Torun, Majid Ahadi Dolatsara, Madhavan Swaminathan, Tushar Krishna, Sung Kyu Lim

IEEE Trans. Very Large Scale Integr. Syst., 2021

Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach.

Taehwan Kim, Heechun Park, Taewhan Kim

IEEE Trans. Very Large Scale Integr. Syst., 2021

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements.

Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim

ACM Trans. Design Autom. Electr. Syst., 2021

Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement.

Eunsol Jeong, Heechun Park, Jooyeon Jeong, Taewhan Kim

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology.

Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, Taewhan Kim

Proceedings of the 18th International SoC Design Conference, 2021

Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis.

Seyoung Kim, Heechun Park, Jaeha Kim

Proceedings of the 18th International SoC Design Conference, 2021

2020

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.

Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim

IEEE Trans. Very Large Scale Integr. Syst., 2020

Advances in Design and Test of Monolithic 3-D ICs.

Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Jinwoo Kim, Gauthaman Murali, Edward Lee, Daehyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay, Krishnendu Chakrabarty

IEEE Des. Test, 2020

Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs.

Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019

Hybrid asynchronous circuit generation amenable to conventional EDA flow.

Heechun Park, Taewhan Kim

Integr., 2019

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs.

Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty, Sung Kyu Lim

Proceedings of the 24th IEEE European Test Symposium, 2019

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.

Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, Sung Kyu Lim

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.

Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Structure optimizations of neuromorphic computing architectures for deep neural network.

Heechun Park, Taewhan Kim

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2016

Synthesizing Asynchronous Circuits toward Practical Use.

Heechun Park, Taewhan Kim

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015

Synthesis of TSV Fault-Tolerant 3-D Clock Trees.

Heechun Park, Taewhan Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2013

Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees.

Heechun Park, Taewhan Kim

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013