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Junyan Bi

Orcid: 0009-0005-3285-8188

According to our database1, Junyan Bi authored at least 3 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth.
[BibTeX]
[DOI]
Junyan Bi
,
Hao Xu
,
Tenghao Zou
,
Yaxin Zeng
,
Yechen Tian
,
Weitao He
,
Junjie Gu
,
Ziyang Jiao
,
Shubin Liu
,
Zhangming Zhu
,
Na Yan
IEEE J. Solid State Circuits, August, 2025

A 12-bit 2GS/s current-steering DAC with 27 mW power consumption in 28 nm CMOS.
[BibTeX]
[DOI]
Beiqi Duan
,
Junyan Bi
,
Hao Xu
,
Guoyu Li
,
Yechen Tian
,
Na Yan
Microelectron. J., 2025

2024
5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression.
[BibTeX]
[DOI]
Hao Xu
,
Junyan Bi
,
Tenghao Zou
,
Weitao He
,
Yaxin Zeng
,
Junjie Gu
,
Ziyang Jiao
,
Shubin Liu
,
Zhangming Zhu
,
Na Yan
Proceedings of the IEEE International Solid-State Circuits Conference, 2024


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