Yechen Tian

Orcid: 0009-0002-1140-5823

According to our database1, Yechen Tian authored at least 8 papers between 2025 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Efficient Time-Skew Calibration for Time-Interleaved ADC via Matrix Binary Decomposition and Increment-Based Adaption.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2026

A 28-nm 8-28-GHz Eight-Phase Clock Generator Using an Injection-Locked Dual-Feedback Ring Oscillator.
IEEE J. Solid State Circuits, January, 2026

2025
A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth.
IEEE J. Solid State Circuits, August, 2025

Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver.
IEEE Trans. Very Large Scale Integr. Syst., March, 2025

A 2 MHz-BW 80.6 dB-SNDR 95.9 dB-SFDR 2nd-order noise-shaping SAR using open-loop Gm-R amplifier.
Microelectron. J., 2025

A 12-bit 2GS/s current-steering DAC with 27 mW power consumption in 28 nm CMOS.
Microelectron. J., 2025

7.10 An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025


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