Hao Xu

Orcid: 0000-0002-0044-1231

Affiliations:
  • University of California at Los Angeles, Electrical Engineering Department, CA, USA


According to our database1, Hao Xu authored at least 17 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier.
IEEE J. Solid State Circuits, October, 2023

A 6-12 GHz Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.
IEEE J. Solid State Circuits, 2023

Analysis and Modeling of Non-ideal Effects in SAR ADC.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

An ADPLL Design Model Based on LoRa IoT Application.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A High Speed, Low Power and Low Phase Noise Divider for Wideband Application.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
A 6-18GHz Low-Noise Amplifier Using Noise Canceling Technique in 130-nm CMOS PD-SOI.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW.
Proceedings of the 47th ESSCIRC 2021, 2021

2019
Analysis and Design of Regenerative Comparators for Low Offset and Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017
Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2015
A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers.
IEEE J. Solid State Circuits, 2015

2014
3.6 A noise-cancelling receiver with enhanced resilience to harmonic blockers.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Understanding the regenerative comparator circuit.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014


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