Hao Xu
Orcid: 0000-0002-0044-1231Affiliations:
- University of California at Los Angeles, Electrical Engineering Department, CA, USA
According to our database1,
Hao Xu authored at least 38 papers
between 2014 and 2026.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2026
A 4-GHz Ring-VCO-Based Wideband Double-Sampling PLL With -88.2-dBc Reference Spur, 119-fs<sub>RMS</sub> Jitter and -244.1-dB FOM.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2026
Efficient Time-Skew Calibration for Time-Interleaved ADC via Matrix Binary Decomposition and Increment-Based Adaption.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2026
A 28-nm 8-28-GHz Eight-Phase Clock Generator Using an Injection-Locked Dual-Feedback Ring Oscillator.
IEEE J. Solid State Circuits, January, 2026
A 17-39GHz Transformer-Based Noise-Cancelling LNA with 2.7-4.3dB Noise Figure in 28nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A Compact 0.2-19GHz Zero-IF Reconfigurable Quadrature Transmitter with Dual-Band Selection in 28nm CMOS Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A 0.65V 10-to-21.5GHz Time-amplifying-based Sampling PLL Achieving 41.3-67.3fs jitter and -255dB Peak FoMT.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 10GHz Double-Edge Sampling PLL with 12.8fsrms Jitter and -257.8dB FoMJ in 65nm CMOS Process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
A 0.2-19GHz Zero-IF Reconfigurable Quadrature Transmitter With T-Coil Matching Network.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2025
A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth.
IEEE J. Solid State Circuits, August, 2025
Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025
A 25-31-GHz Compact True Power Detector With >33-dB Dynamic Range and Intrinsic Phase Offset Compensation in 40-nm Bulk CMOS.
IEEE J. Solid State Circuits, May, 2025
An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2025
Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver.
IEEE Trans. Very Large Scale Integr. Syst., March, 2025
A 2 MHz-BW 80.6 dB-SNDR 95.9 dB-SFDR 2nd-order noise-shaping SAR using open-loop Gm-R amplifier.
Microelectron. J., 2025
Microelectron. J., 2025
19.11 A 13GHz Charge-Pump PLL Achieving 15.8fs<sub>rms</sub> Integrated Jitter and -98.5dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024
A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier.
IEEE J. Solid State Circuits, October, 2023
A 6-12 GHz Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.
IEEE J. Solid State Circuits, 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 26-30GHz Digitally-Controlled Variable Gain Power Amplifier with Phase Compensation and Third Order Nonlinearity Cancellation Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
2021
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW.
Proceedings of the 47th ESSCIRC 2021, 2021
An 800MS/s, 6.7b ENOB Bootstrap Switching S/H IC for Wideband Direct RF Sub-Sampling Receiver in 45 nm CMOS.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2015
IEEE J. Solid State Circuits, 2015
2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014