Shubin Liu

Orcid: 0000-0002-9942-0069

Affiliations:
  • Xidian University, School of Microelectronics, Xi'an, China


According to our database1, Shubin Liu authored at least 161 papers between 2012 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
A 65.5-dB SNDR 100-MS/s Pipelined-SAR ADC With Nested Negative-C and Dynamic Auto-Zeroing Residue Amplifier Achieving ≤ 2.2-dB ΔSNDR Over -20 °C to 125 °C.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

A Single-Channel 1-3 MASH SAR-Assisted Pipeline ADC With Residue Amplifier Error Shaping.
IEEE J. Solid State Circuits, May, 2026

A 0.0006-mm<sup>2</sup>, 0.13-pJ/bit, 9-21-Gb/s Sub-Sampling CDR With Inverter-Based Frequency Multiplier and Embedded 1:3 DEMUX in 65-nm CMOS.
IEEE J. Solid State Circuits, May, 2026

A 12-bit 200-MS/s SAR ADC With Capacitor-Reuse-Based Redundant Weighting Technique.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2026

Offset-Immune Split-LSB Weight Calibration for Capacitor Mismatch and Gain Nonlinearity in Pipelined SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2026

Design and analysis of a wideband low-fractional-spur, low-jitter Fractional-N digital PLL.
Microelectron. J., 2026

A body-gate dynamically floated SPDT switch enabled by 53 nW self-clocked charge pump for low-power IoT applications.
Microelectron. J., 2026

A 75× scalable analog front-end with continuous bandwidth/power reconfigurability for bio-potential signal acquisition.
Microelectron. J., 2026

Analysis and design of a sample-and-hold circuit with enhanced dual-noise-cancellation technique.
Microelectron. J., 2026

A 56-Gb/s NRZ sub-sampling CDR with improved gilbert-based frequency multiplier in 28 nm CMOS.
Microelectron. J., 2026

A 53 dB ripple reduction ratio, 0.68 μ V r m s noise bio-signal analog-front-end with a successive approximation ripple reduction loop.
Microelectron. J., 2026

A full-rate 8.2-to-15.1-Gb/s reference-less CDR using low-cost SAR-based frequency acquisition technique achieving 265ns acquisition time.
Microelectron. J., 2026

A 97.7 dB-SNDR 1 MS/s power/bandwidth scalable exponential-incremental noise-shaping pipeline ADC.
Microelectron. J., 2026

An 18-bit 97.2-μW 40-kSPS Single-Rate Scalable Switched-Capacitor Zoom ADC With Intrinsic DAC Mismatch Immunity and Tri-Level CDAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 64GS/s 8b 64× Time-Interleaved SAR ADC Achieving 33.8dB SNDR at 26GHz in 28nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 112Gb/s DAC-Based PAM-4 Transmitter with Fast Automatic Retiming Clock Phase Optimization and 6-Tap FFE in 28nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 91.4-dB SNDR 200-kSPS Exponential-Incremental ADC with an Open-Loop Ratio-Based Floating Inverter Dynamic Amplifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 0.07-mm<sup>2</sup> 32.7-kHz Frequency Reference with Aging Calibration Embedded 1-second Timer Scoring 22% Residual Error After 500-Hour Aging at 150°C in 28-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 15-Bit 22-μW 3.91-aF Power/Measurement-Time Scalable Direct Capacitance-to-Digital Converter with Closed-Loop Ratio-Based Floating Inverter Dynamic Amplifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 1GS/s 8b 2× Time-Interleaved SAR ADC with Speed-Enhanced Techniques in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A PN-Assisted Dynamic-Window Interstage Gain Calibration for Pipeline-SAR ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A Single-Ended Tri-Mode PAM2/3/4 Transceiver Front-End Achieving 0.437/0.302/0.314 pJ/bit Energy Efficiency for D2D Interconnection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 0.65V 10-to-21.5GHz Time-amplifying-based Sampling PLL Achieving 41.3-67.3fs jitter and -255dB Peak FoMT.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A 1.6-to-16 GHz Sub-1-LSB INLpp 7-bit Phase Interpolator Using Constant-Load Unit with Trimming-Free Digital Calibration in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A Single-Channel 12GS/s 7b Time-Domain ADC Incorporating Self-Adaptive Time Amplifier Achieving >16.1GHz ERBW in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A Timing-Skew-Free 12-bit 4-GS/s Pipelined TI-SAR ADC with a T/H-Based TI MDAC and a Combined Bit-Weight and Offset Background Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A 10GHz Double-Edge Sampling PLL with 12.8fsrms Jitter and -257.8dB FoMJ in 65nm CMOS Process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025
A Low-Noise Class-F<sub>23</sub> VCO With Harmonic Resonance Expansion and 2nd/3rd-Harmonic Outputs for Multiband mm-Wave Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

An 8-bit 5-GS/s Single-Channel Hybrid ADC With a λ/4 Transmission Line Based Time Quantizer.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2025

A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth.
IEEE J. Solid State Circuits, August, 2025

An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme.
IEEE J. Solid State Circuits, July, 2025

Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC.
IEEE Trans. Very Large Scale Integr. Syst., June, 2025

A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration.
IEEE Trans. Very Large Scale Integr. Syst., May, 2025

A -79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025

A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst., March, 2025

A 36.8-μW 66 nV/√Hz 85.7 dB-System-SNDR Reconfigurable Single-Channel ExG Acquisition System for Bio-Sensor Modules.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2025

A 0.4-V 500-kHz FLL With Reused TDA-Based Calibration and OTA-Accelerated Technique in 65-nm CMOS for Sleep Timer.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage.
IEEE J. Solid State Circuits, January, 2025

A 10-bit 4 GS/s Pipelined-SAR ADC based on loop-unrolled and partial-interleaving.
Microelectron. J., 2025

A 2nd-order delta-sigma capacitance-to-digital converter with an embedded error-feedback exponential-incremental noise-shaping SAR quantizer.
Microelectron. J., 2025

Exponential-incremental quantization-based calibration for capacitor mismatch in high-precision SAR ADCs.
Microelectron. J., 2025

Load-driven inductive peaking design for broad band continuous-time linear equalizer.
Microelectron. J., 2025

Withdrawal notice to "A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator" [Microelectron. J. 166 (2025) 106872].
Microelectron. J., 2025

A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator.
Microelectron. J., 2025

Design and analysis of an ultra-wideband quad-mode quad-core oscillator with mode ambiguity elimination.
Microelectron. J., 2025

A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input.
Microelectron. J., 2025

A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units.
Microelectron. J., 2025

A 0.0013-mm2 7-bit 2-GS/s time-domain 4-bit/cycle SAR ADC with the input-recoverable constant-current VTC.
Microelectron. J., 2025

The sampling network for a 16-channel time-interleaved ADC.
Microelectron. J., 2025

Power-efficient SAR ADC with noise-reduction scheme based on kT/C noise cancellation and adaptive tracking averaging.
Microelectron. J., 2025

A linear chirp generator with 2nd DPD technique based on a Type-III SPLL.
Microelectron. J., 2025

A design of 96 GS/s 7-bit DAC for high-speed wireline transmitter in 28-nm CMOS.
Microelectron. J., 2025

Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection.
Microelectron. J., 2025

A 1-V 3.9-5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and -76-dBc reference spur.
Microelectron. J., 2025

A reference-free and derivative-insensitive all-digital calibration technique for timing-skew in TI-ADCs.
Sci. China Inf. Sci., 2025

A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

19.11 A 13GHz Charge-Pump PLL Achieving 15.8fs<sub>rms</sub> Integrated Jitter and -98.5dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

An 18-Bit 183.9dB-FoMS, DR MES/Calibration-Free Scalable Zoom ADC Using Fully Passive Coarse Modulator and Gain-Linearity-Enhanced FIA with Sub-1ppm-THD at Full Scale Input in 65-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based TLSB PVT Variation Calibration and VTC Gain Self-Tracking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A 0.7-V 26.2-28.5 GHz Dual-Loop Double-Sampling PLL with Floating Capacitor OTA Based Gm-CP Achieving a 45.4-fsRMS Jitter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A 66.7dB-SNDR Pipelined-SAR ADC with On-Chip Bit-Weight Calibration Achieving ⃤SNDR<2.4dB Across PVT Variations.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024
A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor.
IEEE J. Solid State Circuits, November, 2024

A 182.9-dB FoM 108.2-dB SFDR Power/Bandwidth Configurable Fully Dynamic Switched-Capacitor Zoom ADC With Interstage Leakage Shaping.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

A Wideband Input Buffer Based on Cascade Complementary Source Follower.
IEEE Trans. Very Large Scale Integr. Syst., May, 2024

A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fs<sub>rms</sub> Integrated Jitter and -250.8-dB FOM<sub>PLL</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

A -64.3 dB THD, 26 nV/√ Hz Bio-Potential Readout Analog-Front-End Amplifier With a Gm-C Integrator-Implanted DC Servo Loop, and a Bulk-Driven Ripple Reduction Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

A wideband low power RF Receiver Front-End for Internet-of-Things applications.
Microelectron. J., February, 2024

A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications.
Microelectron. J., February, 2024

High Power-Efficiency Readout Circuit for MEMS Capacitive Accelerometer.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A 14b 180MS/s Pipeline-SAR ADC With Adaptive-Region-Selection Technique and Gain Error Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

LUT-Assisted Particle Swarm Optimization-Based Bit-Weight Calibration for SAR ADCs.
IEEE Trans. Instrum. Meas., 2024

A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm.
IEEE Trans. Instrum. Meas., 2024

A chopper instrumentation amplifier with discrete-time compensation based on current generation unit to eliminate electrode DC offset.
Microelectron. J., 2024

A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators.
Microelectron. J., 2024

An instrumentation amplifier with series switch pseudo resistor DC-servo loop realizing 0.16-Hz high-pass corner.
Microelectron. J., 2024

An auto-zeroing chopper-stabilized capacitively coupled instrumentation amplifier with 25-Vpp common-mode interference tolerance.
Microelectron. J., 2024

Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS.
Microelectron. J., 2024

A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test.
Microelectron. J., 2024

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique.
Microelectron. J., 2024

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry.
Microelectron. J., 2024

A 2nd-order noise-shaping SAR-assisted pipeline ADC with order-boosted gain-error-shaping.
Microelectron. J., 2024

A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique.
Sci. China Inf. Sci., 2024

A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS.
Sci. China Inf. Sci., 2024

A wide load-range OTA using a digitally assisted compensating technique.
Sci. China Inf. Sci., 2024

5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Low-Cost Linearity Testing of High-Resolution ADCs Using Segmentation Modeling and Partial Polynomial Fitting.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm<sup>2</sup> Area.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers.
Proceedings of the IEEE International Conference on Integrated Circuits, 2024

A 0.64mm<sup>2</sup>Sensor Size, 32.5μg/√Hz Noise Floor, High Efficiency MEMS Capacitive Accelerometer Using High-Voltage Pulse Excitation Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A 737nA Always-On MEMS Gyroscope with 5.45ms Start-up Time Using Burst Mode PLL Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A 2.4 GHz Ultra-Low-Power Low-Voltage Temperature-Stable Transmitter for Biosensing Applications.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2024

A 0.0006-mm<sup>2</sup> 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

A 14b Calibration-Free Pipelined SAR ADC Using a Single-Stage Gain Boost FIA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

A 14.6-ENOB Second-Order Noise-Shaping SAR ADC With kT/C Noise Shifting.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

An Energy-Efficient Look-up Table Framework for Super Resolution on FPGA.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

A High Precision CV Control Scheme for Low Power AC-DC BUCK Converter Controller.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

A 44-μW, 91.3-dB SNDR DT Δ Σ Modulator With Second-Order Noise-Shaping SAR Quantizer.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

A 0.26 μVrms instrumentation amplifier based on discrete-time DC servo loop with successive-approximation-compensation technique and Chopper DAC Array.
Microelectron. J., September, 2023

An offset and gain error calibration method in high-precision SAR ADCs.
Microelectron. J., September, 2023

An All-Digital Background Calibration Technique for M-Channel Downsampling Time-Interleaved ADCs Based on Interpolation.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

A 63 μg/√Hz Noise Floor and 14 pJ Power Efficiency Open-Loop MEMS Capacitive Accelerometer Using Closed-Loop Hybrid Dynamic Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

A 100- to- 10-kHz 5.4- to- 216- μW Power-Efficient Readout Circuit Employing Closed-Loop Dynamic Amplifier for MEMS Capacitive Accelerometer.
IEEE J. Solid State Circuits, 2023

A Single-Channel 70dB-SNDR 100MHz-BW 4<sup>th</sup>-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 0.012mm<sup>2</sup> 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

An 83.6dB-SNDR 101.6dB-SFDR 4<sup>th</sup>-Order Noise-Shaping SAR with 2<sup>nd</sup>-Order Nonlinearity Error Shaping.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A $142.8-\mu \text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage Shaping.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 77.8dB-SNDR 25MHz-BW 2<sup>nd</sup>-order NS Pipelined SAR ADC with 4<sup>th</sup>-order Gain-Error-Shaping.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
Correlated Double Amplifying Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer.
IEEE Trans. Instrum. Meas., 2022

A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 0.018 %/V Line Sensitivity Voltage Reference With -82.46 dB PSRR at 100 Hz for Bio-Potential Signals Readout Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems.
IEEE Trans. Biomed. Circuits Syst., 2022

Capacitance-to-voltage converter employing parallel-series passive charge integrator for low noise power efficient MEMS capacitive sensor.
Microelectron. J., 2022

A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS.
Microelectron. J., 2022

Radio frequency analog-to-digital converters: Systems and circuits review.
Microelectron. J., 2022

A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration.
Microelectron. J., 2022

An efficient EEGNet processor design for portable EEG-Based BCIs.
Microelectron. J., 2022

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations.
IEEE J. Solid State Circuits, 2022

Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs.
Circuits Syst. Signal Process., 2022

A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs.
Microelectron. J., 2021

A 2.6 GΩ, 1.4 μV<sub>rms</sub> current-reuse instrumentation amplifier for wearable electrocardiogram monitoring.
Microelectron. J., 2021

A 79.1dB-SNDR 20MHz-BW 2<sup>nd</sup>-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 7b 400 ​MS/s pipelined SAR ADC in 65 ​nm CMOS.
Microelectron. J., 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.
IEEE J. Solid State Circuits, 2020

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency Compensation Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC.
J. Circuits Syst. Comput., 2019

2018
Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs.
J. Circuits Syst. Comput., 2018

A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage.
Microelectron. J., 2017

Analysis and optimal distribution scheme for SAR-VCO ADCs.
Microelectron. J., 2017

2016
A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS.
Microelectron. J., 2016

An automatic mode low-jitter pulsewidth control loop with broadband operation frequency.
Microelectron. J., 2016

An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS.
Microelectron. J., 2016

2013
A Low Offset Comparator for High Speed Low Power ADC.
J. Circuits Syst. Comput., 2013

A low-jitter pulsewidth control loop with high supply noise rejection.
IEICE Electron. Express, 2013

2012
A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference.
IEICE Electron. Express, 2012


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