Yasuyuki Tanabe

According to our database, Yasuyuki Tanabe authored at least 4 papers between 1994 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2002

A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell.

Nobutaro Shibata, Mayumi Watanabe, Yasuyuki Tanabe

IEEE J. Solid State Circuits, 2002

1999

A single-chip fingerprint sensor and identifier.

Satoshi Shigematsu, Hiroki Morimura, Yasuyuki Tanabe, Takuya Adachi, Katsuyuki Machida

IEEE J. Solid State Circuits, 1999

1997

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits.

Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada

IEEE J. Solid State Circuits, 1997

1994

BiCMOS circuit technology for a 704 MHz ATM switch LSI.

Yusuke Ohtomo, Sadayuki Yasuda, Minoru Togashi, Massyuki Ino, Yasuyuki Tanabe, Jun-ichi Inoue, Masafumi Nogawa, Sshigeki Hino

IEEE J. Solid State Circuits, May, 1994