Jyh-Herng Wang

According to our database, Jyh-Herng Wang authored at least 4 papers between 1994 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design.

Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, Jyh-Herng Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Simultaneous block and I/O buffer floorplanning for flip-chip design.

Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A routing algorithm for flip-chip design.

Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

1994

An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits.

Jyh-Herng Wang, Jen-Teng Fan, Wu-Shiung Feng

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994