Wu-Shiung Feng

According to our database, Wu-Shiung Feng authored at least 54 papers between 1988 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A Simple Drain Current Model for MOS Transistors with the Lorentz Force Effect.

Hwang-Cherng Chow, Prasenjit Chatterjee, Wu-Shiung Feng

Sensors, 2017

2016

Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing Application.

Prasenjit Chatterjee, Hwang-Cherng Chow, Wu-Shiung Feng

Sensors, 2016

2008

Model-order reductions for MIMO systems using global Krylov subspace methods.

Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng

Math. Comput. Simul., 2008

A 24GHz low-power CMOS receiver design.

Chen-Yuan Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng, Wu-Shiung Feng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

On the Equivalent of Structure Preserving Reductions Approach and Adjoint Networks Approach for VLSI Interconnect Reductions.

Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Lyapunov-Based Error Estimations of MIMO Interconnect Reductions by Using the Global Arnoldi Algorithm.

Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Applications of AOGL Model-Order Reduction Techniques in Interconnect Analysis.

Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

XNOR-based double-edge-triggered flip-flop for two-phase pipelines.

Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng

IEEE Trans. Circuits Syst. II Express Briefs, 2006

A Brief Comparison of Two-phase and NOR-based Four-phase Pipelined Asynchronous Systems.

Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng

J. Inf. Sci. Eng., 2006

An Adjoint Network Approach for RLCG Interconnect Model Order Reductions.

Chia-Chi Chu, Herng-Jer Lee, Ming-Hong Lai, Wu-Shiung Feng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm.

Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng

IEICE Trans. Electron., 2006

The Multiple Point Global Lanczos Method for Multiple-Inputs Multiple-Outputs Interconnect Order Reductions.

Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

MIMO interconnects order reductions by using the global Arnoldi algorithm.

Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

The global Lanczos method for MIMO interconnect order reductions.

Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Model-Order Reduction Algorithm with Structure Preserving Techniques.

Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

The Multiple Point Global Lanczos Method for MIMO Interconnect Model-Order Reductions.

Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

A One-Step Input Matching Method for Cascode CMOS Low-Noise Amplifiers.

Ming-Chang Sun, Ying-Haw Shu, Shing Tenqchen, Wu-Shiung Feng

IEICE Trans. Electron., 2005

Moment Computations of Distributed Coupled RLC Interconnects with Applications to Estimating Crosstalk Noise.

Herng-Jer Lee, Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng

IEICE Trans. Electron., 2005

Perturbation Approach for Order Selections of Two-Sided Oblique Projection-Based Interconnect Reductions.

Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Error Estimations of Arnoldi-Based Interconnect Model-Order Reductions.

Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Interconnect model reductions by using the AORA algorithm with considering the adjoint network.

Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications.

Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk Noise.

Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Applications of tree/link partitioning for moment computations of general lumped RLC networks with resistor loops.

Herng-Jer Lee, Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Generalizations of adjoint networks technique for RLC interconnects model-order reductions.

Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Blind Signal Extraction Algorithm for the License Plate Matching of Vehicle Positioning System.

Shing Tenqchen, Ying-Haw Shu, Ming-Chang Sun, Wu-Shiung Feng

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

An XNOR-based Double-edge-triggered Flip-Flop for Two-phase Pipelines.

Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng

Proceedings of the 2nd International Conference Computing, 2004

2003

Moment Computations of Lumped Coupled RLC Trees with Applications to Estimating Crosstalk Noise.

Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A 2.4 GHz CMOS image-reject low noise amplifier.

Ming-Chang Sun, Shing Tenqchen, Ying-Haw Shu, Wu-Shiung Feng

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Interconnect modeling and sensitivity analysis using adjoint networks reduction technique.

Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Intelligent multipoint Arnoldi (IMA) approximations of FIR filters by low-order linear-phase IIR filters.

Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Pipelining Extended Givens Rotation RLS Adaptive Filters.

Shing Tenqchen, Ji-Horn Chang, Wu-Shiung Feng, Bor-Sheng Jeng

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models.

Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

On-board effective inductance measurement.

Chin Hsia, Ming-Hong Lai, Wu-Shiung Feng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage.

Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Testable design of multiple-stage OTA-C filters.

Cheng-Chung Hsu, Wu-Shiung Feng

IEEE Trans. Instrum. Meas., 2000

A new VLSI architecture without global broadcast for 2-D digital filters.

Lan-Da Van, Chih-Chun Tang, Shing Tenqchen, Wu-Shiung Feng

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Design of a lower-error fixed-width multiplier for speech processing application.

Lan-Da Van, Shuenn-Shyang Wang, Shing Tenqchen, Wu-Shiung Feng, Bor-Shenn Jeng

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A tree-systolic array of DLMS adaptive filter.

Lan-Da Van, Shing Tenqchen, Chia-Hsun Chang, Wu-Shiung Feng

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1995

Relaxation-based transient sensitivity computations for MOSFET circuits.

Chun-Jung Chen, Wu-Shiung Feng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994

New efficient designs for XOR and XNOR functions on the transistor level.

Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng

IEEE J. Solid State Circuits, July, 1994

An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits.

Jyh-Herng Wang, Jen-Teng Fan, Wu-Shiung Feng

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation.

Chung-Jung Chen, Wu-Shiung Feng

Proceedings of the 31st Conference on Design Automation, 1994

1992

An H-V alternating router.

Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

A New Efficient Approach to Multilayer Channel Routing Problem.

Sung-Chuan Fang, Wu-Shiung Feng, Shian-Lang Lee

Proceedings of the 29th Design Automation Conference, 1992

1991

A knowledge-based program for compacting mask layout of integrated circuits.

Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng

Comput. Aided Des., 1991

Transient Sensitivity Computation for Waveform Relaxation Based Timing Simulation.

Chun-Jung Chen, Jyuo-Min Shyu, Wu-Shiung Feng

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems.

Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen

Proceedings of the 28th Design Automation Conference, 1991

1990

Using a multiple storage quad tree on a hierarchical VLSI compaction scheme.

Pei-Yung Hsiao, Wu-Shiung Feng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

An <i>H-V</i> Tile-Expansion Router.

Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng

J. Inf. Sci. Eng., 1990

A new control strategy for an artificial intelligence approach to VLSI layout compaction.

Pei-Yung Hsiao, H. F. Steven Chen, Wu-Shiung Feng

Integr., 1990

Generalized terminal connectivity problem for multilayer layout scheme.

Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng

Comput. Aided Des., 1990

1989

The Control Model for a Knowledge-Based Approach to VLSI Compaction Design.

S. F. Steven Chen, Pei-Yung Hsiao, Wu-Shiung Feng, Shun-Nan Dai, Wen-Zyh Wang

Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

1988

A rule-based compactor for VLSI/CAD mask layout.

Pei-Yung Hsiao, Chen Yung Syau, Wu-Shiung Feng, T. M. Parng, Cheng-Chung Hsu

Proceedings of the Twelfth International Computer Software and Applications Conference, 1988