Kai-Wei Ruan

According to our database, Kai-Wei Ruan authored at least 2 papers between 2014 and 2017.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2017

2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation.

Chua-Chin Wang, Zong-You Hou, Kai-Wei Ruan

IEEE Trans. Circuits Syst. II Express Briefs, 2017

2014

32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation.

Tzung-Je Lee, Kai-Wei Ruan, Chua-Chin Wang

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014