Chandan Kumar Jha

Orcid: 0000-0002-7237-5878

Affiliations:
  • Deutsches Forschungszentrum für Künstliche Intelligenz (DFKI), Bremen, Germany
  • Indian Institute of Technology Bombay, Mumbai, India (former)
  • Indian Institute of Technology Gandhinagar, Gujarat, India


According to our database1, Chandan Kumar Jha authored at least 29 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style.
IEEE Embed. Syst. Lett., December, 2023

MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders.
IEEE Trans. Very Large Scale Integr. Syst., 2023

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.
CoRR, 2023

Finite State Automata Design using 1T1R ReRAM Crossbar.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Benchmarking Multiplier Architectures for MAGIC Based In-Memory Computing.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Analysis of Quantization Across DNN Accelerator Architecture Paradigms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

2022
A Fresh Perspective on DNN Accelerators by Performing Holistic Analysis Across Paradigms.
CoRR, 2022

Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph Analytics.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

A fibre Bragg grating sensor-based instrumented glove for virtual rehabilitation applications.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Data-Aware Cache Management for Graph Analytics.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Analysis of Worst-Case Data Dependent Temporal Approximation in Floating Point Units.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

FPCAM: Floating Point Configurable Approximate Multiplier for Error Resilient Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Energy and Error Analysis Framework for Approximate Computing in Mobile Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Tunable Inexact Subtracters for Division in Image Processing Applications.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

FPAD: A Multistage Approximation Methodology for Designing Floating Point Approximate Dividers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Quality Tunable Approximate Adder for Low Energy Image Processing Applications.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

SEDA - Single Exact Dual Approximate Adders for Approximate Processors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Should We Code Differently When Using Approximate Circuits?
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
A Fiber Bragg Grating Strain Sensor-Based Glove to Accurately Measure the Bend Angle of the Finger Flexed at the Proximal Interphalangeal Joints.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

2016
A Novel Methodology for Design of Cyclic Combinational Circuits.
J. Low Power Electron., 2016


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