Kanan Wang

Orcid: 0009-0008-7062-304X

According to our database1, Kanan Wang authored at least 7 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
A 0.92-pJ/b 112-Gb/s PAM-4 Transmitter With Bandwidth and Linearity Enhanced Quasi-Voltage-Mode Driver and Reconfigurable Three-Tap T/2-T Variable Fractional-Spaced FFE in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

7.9 A 60Gb/s NRZ Burst-Mode CDR with Cross-Injection Locking and Flash Phase Detector Achieving 0.13ns Reconfiguration Time in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

36.5 A Low-Latency 200Gb/s PAM-4 Heterogeneous Transceiver in 0.13μm SiGe BiCMOS and 28nm CMOS for Retimed Pluggable Optics.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2023
A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique.
IET Circuits Devices Syst., January, 2023

A 28/56 Gb/s NRZ/PAM-4 Dual-Mode Transceiver in 28-nm CMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2021
A 130-GBaud 2: 1 Analog Multiplexer in 130-nm SiGe BiCMOS.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020
A 100-Gb/s PAM-4 CTLE in 28-nm CMOS with Coarse-Fine Gain Adjustment.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020


  Loading...