Quan Pan
Orcid: 0000-0001-8704-4505Affiliations:
- Southern University of Science and Technology, School of Microelectronics, Shenzhen, China
- Hong Kong University of Science and Technology, HKUST, Department of electronics and computer engineering, Hong Kong (PhD 2014)
According to our database1,
Quan Pan
authored at least 47 papers
between 2013 and 2024.
Collaborative distances:
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Bibliography
2024
7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique.
IET Circuits Devices Syst., January, 2023
A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 28-Gb/s PAM-4 Fully-Integrated Optical Receiver with High-Speed Silicon Photodetector in 28-nm CMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A Power-Efficient $\boldsymbol{4}-\mathbf{V}_{\mathbf{ppd}}$ 128-Gb/s PAM-4 Optical Modulator Driver with Merged BV Doubler Topology in 130-nm BiCMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 6.15-10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With "Phase Reset" Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS.
IEEE J. Solid State Circuits, 2022
A 200-Gb/s PAM-4 Feedforward Linear Equalizer with Multiple-Peaking and Fixed Maximum Peaking Frequencies in 130nm SiGe BiCMOS.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
A 2×50Gb/s Single-Ended MIMO PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver in 28 nm CMOS.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A 19-48.3-GHz 6<sup>th</sup>-Order Transformer-Based Injection-Locked Frequency Divider With 87.1% Locking Range in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Microelectron. J., 2021
8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
An Area-Efficient Low Quiescent Current Output Capacitor-Less LDO with Fast Transient Response.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Design and Co-Simulation of QPSK and NRZ/PAM-4/PAM-8 VCSEL-Based Optical Links Utilizing an Integrated System Evaluation Engine.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A 720-mVpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 42-dB Ω 25-Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
A 224-Gb/s PAM4 High-Linearity, Energy-Efficiency Differential to Single-Ended Driver in 130-nm SiGe BiCMOS.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
2019
A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 60GHz 4Gb/s fully integrated NRZ-to-QPSK modulator SoC for backhaul links in fiber-wireless networks.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
A 26-28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the ESSCIRC 2014, 2014
2013
A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013