Kanan Wang

According to our database1, Kanan Wang authored at least 4 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique.
IET Circuits Devices Syst., January, 2023

A 28/56 Gb/s NRZ/PAM-4 Dual-Mode Transceiver in 28-nm CMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2021
A 130-GBaud 2: 1 Analog Multiplexer in 130-nm SiGe BiCMOS.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020
A 100-Gb/s PAM-4 CTLE in 28-nm CMOS with Coarse-Fine Gain Adjustment.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020


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