Kanchan Manna

Orcid: 0000-0002-2325-8093

According to our database1, Kanchan Manna authored at least 22 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2023
Fault-aware routing approach for mesh-based Network-on-Chip architecture.
Integr., November, 2023

Application Mapping Onto Manycore Processor Architectures Using Active Search Framework.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023

2022
Application driven routing for mesh based Network-on-Chip architectures.
Integr., 2022

2019
Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems.
ACM J. Emerg. Technol. Comput. Syst., 2019

Thermal-Aware Partitioning and Encoding of Power-Gated FSM.
J. Circuits Syst. Comput., 2019

2018
Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design.
IEEE Trans. Computers, 2018

2016
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design.
ACM Trans. Embed. Comput. Syst., 2016

Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip.
J. Circuits Syst. Comput., 2015

Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation.
Int. J. High Perform. Syst. Archit., 2015

TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip.
J. Syst. Archit., 2014

Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A spare router based reliable Network-on-Chip design.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2012
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison.
Int. J. High Perform. Syst. Archit., 2012

2009
A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic.
Proceedings of the ARTCom 2009, 2009

2008
Mesh-of-Tree Based Scalable Network-on-Chip Architecture.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

A Novel Technique to Reduce both Leakage and Peak Power during Scan Testing.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008


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