Kaoru Okazaki

According to our database, Kaoru Okazaki authored at least 6 papers between 1981 and 1998.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

1998

A new router for reducing "antenna effect" in ASIC design.

Hiroshi Shirota, Toshiyuki Sadakane, Masayuki Terai, Kaoru Okazaki

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

A CMOS cell generation system for two-dimensional transistor placement.

Satoshi Shibatani, Toshiyuki Sadakane, Hiroomi Nakao, Masayuki Terai, Kaoru Okazaki

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1983

Delay-Time Modeling for ED MOS Logic LSI.

Takeshi Tokuda, Kaoru Okazaki, Kazuhiro Sakashita, Isao Ohkura, Tatsuya Enomoto

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

A multiple media delay simulator for MOS LSI circuits.

Kaoru Okazaki, Tomoko Moriya, Toshihiko Yahara

Proceedings of the 20th Design Automation Conference, 1983

1981

Efficient Logic Verification and Test Validation for MOS LSI Circuits.

Kaoru Okazaki, Toshihiko Yahara

Proceedings of the Proceedings International Test Conference 1981, 1981

An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3.

Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana

Proceedings of the 18th Design Automation Conference, 1981