Shinichi Murai

According to our database1, Shinichi Murai authored at least 12 papers between 1978 and 1993.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

1993
Tri-state bus conflict checking method for ATPG using BDD.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1990
Rule-based testability rule check program.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989
MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Test generation for sequential circuits using individual initial value propagation.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
ASTA: LSI Design Management System.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1985
LORES-2: A Logic Reorganization System.
IEEE Des. Test, 1985

PATEGE: an automatic DC parametric test generation system for series gated ECL circuits.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1983
Test generation for scan design circuits with tri-state modules and bidirectional terminals.
Proceedings of the 20th Design Automation Conference, 1983

1981
An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3.
Proceedings of the 18th Design Automation Conference, 1981

An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2.
Proceedings of the 18th Design Automation Conference, 1981

1979
A hierarchical placement procedure with a simple blocking scheme.
Proceedings of the 16th Design Automation Conference, 1979

1978
LORES - Logic Reorganization System.
Proceedings of the 15th Design Automation Conference, 1978


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