Karl Norling

According to our database, Karl Norling authored at least 4 papers between 2012 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 0.13-μm HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication.

Lucrezia Navarin, Karl Norling, Marco Parenzan, Alexander Uran, Stefano Ruzzu, Krithika Rathinam, Andrea Neviani, Andrea Bevilacqua

IEEE J. Solid State Circuits, June, 2026

2025

A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication.

Lucrezia Navarin, Karl Norling, Marco Parenzan, Stefano Ruzzu, Andrea Neviani, Andrea Bevilacqua

IEEE Solid State Circuits Lett., 2025

2012

An Optimized Driver for SiC JFET-Based Switches Enabling Converter Operation With More Than 99% Efficiency.

Karl Norling, Christian Lindholm, Dieter Draxelmayr

IEEE J. Solid State Circuits, 2012

An optimized driver for SiC JFET-based switches delivering more than 99% efficiency.

Karl Norling, Christian Lindholm, Dieter Draxelmayr

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012