Marco Parenzan

According to our database, Marco Parenzan authored at least 2 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 0.13-μm HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication.

Lucrezia Navarin, Karl Norling, Marco Parenzan, Alexander Uran, Stefano Ruzzu, Krithika Rathinam, Andrea Neviani, Andrea Bevilacqua

IEEE J. Solid State Circuits, June, 2026

2025

A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication.

Lucrezia Navarin, Karl Norling, Marco Parenzan, Stefano Ruzzu, Andrea Neviani, Andrea Bevilacqua

IEEE Solid State Circuits Lett., 2025