Andrea Bevilacqua
Orcid: 0000-0002-5664-9197
According to our database1,
Andrea Bevilacqua
authored at least 89 papers
between 2003 and 2024.
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Bibliography
2024
IEEE J. Solid State Circuits, January, 2024
2023
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.
IEEE J. Solid State Circuits, March, 2023
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
2022
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise.
IEEE J. Solid State Circuits, 2022
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications.
IEEE J. Solid State Circuits, 2022
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time.
IEEE J. Solid State Circuits, 2022
A 68.6fs<sub>rms</sub>-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
2020
IEEE J. Solid State Circuits, 2020
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019
A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS.
Proceedings of the 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019
2018
Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm<sup>2</sup> Area w/ 2D Digital-Pre-Distortion and Package Combiner.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the Computational Science - ICCS 2018, 2018
2017
13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE J. Solid State Circuits, 2016
A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 40-67 GHz Power Amplifier With 13 dBm ℙ<sub>SAT</sub> and 16% PAE in 28 nm CMOS LP.
IEEE J. Solid State Circuits, 2015
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs.
Proceedings of the Nordic Circuits and Systems Conference, 2015
Proceedings of the ESSCIRC Conference 2015, 2015
2014
Energy-efficient ultra-wideband impulse radios for short-range low-data rate communications.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the ESSCIRC 2014, 2014
2013
A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer.
IEEE J. Solid State Circuits, 2013
A 2-to-16GHz 204mW 3mm-resolution stepped-frequency radar for breast-cancer diagnostic imaging in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the ESSCIRC 2013, 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
IEEE J. Solid State Circuits, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Integrated transceivers for UWB breast cancer imaging: Architecture and circuit constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
IEEE J. Solid State Circuits, 2010
A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems.
IEEE J. Solid State Circuits, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 μm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Sigma Delta Modulator and a Flash Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2005
2004
IEEE J. Solid State Circuits, 2004
2003
System analysis and circuit design of CMOS integrated wireless receivers for WCDMA and UWB applications.
PhD thesis, 2003