Andrea Neviani

According to our database1, Andrea Neviani authored at least 64 papers between 1990 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
A 130-nm CMOS Dual Input-Polarity DC-DC Converter for Low-Power Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation.
IEEE J. Solid State Circuits, 2016

A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
Energy-efficient ultra-wideband impulse radios for short-range low-data rate communications.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

2013
A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer.
IEEE J. Solid State Circuits, 2013

A 2-to-16GHz 204mW 3mm-resolution stepped-frequency radar for breast-cancer diagnostic imaging in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Low-power ultra-Wide-Band Impulse Radio transceivers for short range communications.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

A SiGe bipolar VCO for backhaul E-band communication systems.
Proceedings of the 38th European Solid-State Circuit conference, 2012

A 1.75-15 GHz stepped frequency receiver for breast cancer imaging in 65 nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13 μm CMOS.
IEEE J. Solid State Circuits, 2011

Integrated transceivers for UWB breast cancer imaging: Architecture and circuit constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A 0.06 mm <sup>2</sup> 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-power UWB transmitter using a combined mixer and power amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A digitally programmable ring oscillator in the UWB range.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems.
IEEE J. Solid State Circuits, 2009

A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking.
IEEE J. Solid State Circuits, 2008

Analog decoding of trellis coded modulation for multi-level flash memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An energy-detector for non-coherent impulse-radio UWB receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Design of broadband inductorless LNAs in ultra-scaled CMOS technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Transformer-Based Dual-Mode Voltage-Controlled Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

An Integrated Solution for Suppressing WLAN Signals in UWB Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 0.18-µm CMOS Squarer Circuit for a Non-Coherent UWB Receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Quadrature VCOs Based on Coupled PLLs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code.
IEEE Trans. Commun., 2006

An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Sigma Delta Modulator and a Flash Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
A 1.8-μW sigma-delta modulator for 8-bit digitization of cardiac signals in implantable pacemakers operating down to 1.8 V.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

A multi-mode Sigma-Delta analog-to-digital converter for GSM, UMTS and WLAN.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code.
Proceedings of IEEE International Conference on Communications, 2005

2004
A fully integrated dual-channel log-domain programmable preamplifier and filter for an implantable cardiac pacemaker.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

An analog turbo decoder for the UMTS standard.
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004

A low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block turbo code.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Performance optimization in micro-power, low-voltage log-domain filters in pure CMOS technology.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

An analog decoder for concatenated magnetic recording schemes.
Proceedings of the IEEE International Conference on Communications, 2002

2001
Modeling of Substrate Noise Injected by Digital Libraries.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Realistic Worst-Case Modeling by Performance Level Principal Component Analysis.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1996
A new structure for video-rate 2D SC FIR filters.
Proceedings of the 8th European Signal Processing Conference, 1996

1990
Physical models for heterostructure FET simulation.
Eur. Trans. Telecommun., 1990


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