Karthik Shivashankar
Orcid: 0009-0001-8508-2978
According to our database1,
Karthik Shivashankar
authored at least 20 papers
between 2010 and 2025.
Collaborative distances:
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Bibliography
2025
Unravelling Technical debt topics through Time, Programming Languages and Repository.
CoRR, April, 2025
CoRR, April, 2025
Scalability and Maintainability Challenges and Solutions in Machine Learning: Systematic Literature Review.
CoRR, April, 2025
CoRR, April, 2025
CoRR, January, 2025
BEACon-TD: Classifying Technical Debt and its types across diverse software projects issues using transformers.
J. Syst. Softw., 2025
Proceedings of the 22nd IEEE/ACM International Conference on Mining Software Repositories, 2025
Proceedings of the 4th IEEE/ACM International Conference on AI Engineering, 2025
2024
CoRR, 2024
Towards Enhancing Task Prioritization in Software Development Through Transformer-Based Issues Classification.
Proceedings of the Product-Focused Software Process Improvement, 2024
2023
Technical Debt Classification in Issue Trackers using Natural Language Processing based on Transformers.
Proceedings of the 2023 ACM/IEEE International Conference on Technical Debt (TechDebt), 2023
2022
Proceedings of the 48th Euromicro Conference on Software Engineering and Advanced Applications, 2022
2021
Smart Municipal Governance System Using Confluence of Technologies in a Developing Country Scenario.
Proceedings of the ICEGOV 2021: 14th International Conference on Theory and Practice of Electronic Governance, Athens, Greece, October 6, 2021
2014
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2011
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation".
IEEE J. Solid State Circuits, 2011
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation.
IEEE J. Solid State Circuits, 2011
2010
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010