David T. Blaauw

According to our database1, David T. Blaauw authored at least 506 papers between 1988 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2012, "For contributions to adaptive and low power circuit design".

Timeline

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Bibliography

2019
Low Complexity, Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low-Power Mobile Vision Applications.
IEEE Trans. Circuits Syst. Video Techn., 2019

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks.
IEEE Micro, 2019

A 1920 $\times$ 1080 25-Frames/s 2.4-TOPS/W Low-Power 6-D Vision Processor for Unified Optical Flow and Stereo Depth With Semi-Global Matching.
J. Solid-State Circuits, 2019

A 42 nJ/Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-Ion Batteries.
J. Solid-State Circuits, 2019

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.
J. Solid-State Circuits, 2019

The Internet of Tiny Things: Recent Advances of Millimeter-Scale Computing.
IEEE Design & Test, 2019

A Reference Oversampling Digital Phase-Locked Loop with -240 dB FOM and -80 dBc Reference Spur.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 10mm3 Light-Dose Sensing IoT2 System With 35-To-339nW 10-To-300klx Light-Dose-To-Digital Converter.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 31 pW-to-113 nW Hybrid BJT and CMOS Voltage Reference with 3.6% ±3σ-inaccuracy from 0C to 170 C for Low-Power High-Temperature IoT Systems.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 1.74.12 mm3 Fully Integrated pH Sensor for Implantable Applications using Differential Sensing and Drift-Compensation.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 606μW mm-Scale Bluetooth Low-Energy Transmitter Using Co-Designed 3.5×3.5mm2 Loop Antenna and Transformer-Boost Power Oscillator.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

An Adiabatic Sense and Set Rectifier for Improved Maximum-Power-Point Tracking in Piezoelectric Harvesting with 541% Energy Extraction Gain.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

An 879GOPS 243mW 80fps VGA Fully Visual CNN-SLAM Processor for Wide-Range Autonomous Exploration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 6.4pJ/Cycle Self-Tuning Cortex-M0 IoT Processor Based on Leakage-Ratio Measurement for Energy-Optimal Operation Across Wide-Range PVT Variation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Energy-Efficient Low-Noise CMOS Image Sensor with Capacitor Array-Assisted Charge-Injection SAR ADC for Motion-Triggered Low-Power IoT Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 142nW Voice and Acoustic Activity Detection Chip for mm-Scale Sensor Nodes Using Time-Interleaved Mixer-Based Frequency Scanning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

IoT2 - the Internet of Tiny Things: Realizing mm-Scale Sensors through 3D Die Stacking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware.
Signal Processing Systems, 2018

Harmonium: Ultra Wideband Pulse Generation with Bandstitched Recovery for Fast, Accurate, and Robust Indoor Localization.
TOSN, 2018

Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security.
J. Solid-State Circuits, 2018

iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor.
J. Solid-State Circuits, 2018

A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles.
J. Solid-State Circuits, 2018

Always-On 12-nW Acoustic Sensing and Object Recognition Microsystem for Unattended Ground Sensor Nodes.
J. Solid-State Circuits, 2018

A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector.
J. Solid-State Circuits, 2018

A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin.
J. Solid-State Circuits, 2018

Bioelectronic Interface between Biomolecular Logic Systems and Microelectronics.
IJUC, 2018

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks.
CoRR, 2018

A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime Replica Calibration.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 224 PW 260 PPM/°C Gate-Leakage-Based Timer for Ultra-Low Power Sensor Nodes with Second-Order Temperature Dependency Cancellation.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A1920 × 1080 25FPS, 2.4TOPS/W Unified Optical Flow and Depth 6D Vision Processor for Energy-Efficient, Low Power Autonomous Navigation.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 179-Lux Energy-Autonomous Fully-Encapsulated 17-mm3 Sensor Node with Initial Charge Delay Circuit for Battery Protection.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 2.2 NEF Neural-Recording Amplifier Using Discrete-Time Parametric Amplification.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 0.04MM316NW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 2.5nJ duty-cycled bridge-to-digital converter integrated in a 13mm3 pressure-sensing system.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

GenAx: A Genome Sequencing Accelerator.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

A receiver/antenna co-design for a 1.5mJ per fix fully-integrated 10×10×6mm3 GPS logger.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices.
IEEE Trans. VLSI Syst., 2017

Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part II - Data Communication, Energy Harvesting, Power Management, and Digital Circuits.
IEEE Trans. on Circuits and Systems, 2017

Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part I - Analog Circuit Techniques.
IEEE Trans. on Circuits and Systems, 2017

Autonomous Microsystems for Downhole Applications: Design Challenges, Current State, and Initial Test Results.
Sensors, 2017

Hardware Designs for Security in Ultra-Low-Power IoT Systems: An Overview and Survey.
IEEE Micro, 2017

A 20-pW Discontinuous Switched-Capacitor Energy Harvester for Smart Sensor Applications.
J. Solid-State Circuits, 2017

A Fully Integrated Counter Flow Energy Reservoir for Peak Power Delivery in Small Form-Factor Sensor Systems.
J. Solid-State Circuits, 2017

Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC.
J. Solid-State Circuits, 2017

A Subthreshold Voltage Reference With Scalable Output Voltage for Low-Power IoT Systems.
J. Solid-State Circuits, 2017

A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS.
J. Solid-State Circuits, 2017

Impact of FinFET on Near-Threshold Voltage Scalability.
IEEE Design & Test, 2017

RF-Echo: A Non-Line-of-Sight Indoor Localization System Using a Low-Power Active RF Reflector ASIC Tag.
Proceedings of the 23rd Annual International Conference on Mobile Computing and Networking, 2017

Cache automaton.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

9.2 A 0.6nJ -0.22/+0.19°C inaccuracy temperature sensor using exponential subthreshold oscillation dependence.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

22.6 A fully integrated counter-flow energy reservoir for 70%-efficient peak-power delivery in ultra-low-power systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

4.4 A sub-nW 80mlx-to-1.26Mlx self-referencing light-to-digital converter with AlGaAs photodiode.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

7.4 A 915MHz asymmetric radio using Q-enhanced amplifier for a fully integrated 3×3×3mm3 wireless sensor node with 20m non-line-of-sight communication.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Rectified-linear and recurrent neural networks built with spin devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A Programmable Galois Field Processor for the Internet of Things.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Compute Caches.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

A 1.02nW PMOS-only, trim-free current reference with 282ppm/°C from -40°C to 120°C and 1.6% within-wafer inaccuracy.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Low-power switched-capacitor converter design techniques for small IoT systems.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Analog in-memory subthreshold deep neural network accelerator.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Subthreshold voltage reference with nwell/psub diode leakage compensation for low-power high-temperature systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

Cache Automaton: Repurposing Caches for Automata Processing.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Approximate SRAMs With Dynamic Energy-Quality Management.
IEEE Trans. VLSI Syst., 2016

Using Low Cost Erasure and Error Correction Schemes to Improve Reliability of Commodity DRAM Systems.
IEEE Trans. Computers, 2016

Ultralow Power Circuit Design for Wireless Sensor Nodes for Structural Health Monitoring.
Proceedings of the IEEE, 2016

MBus: A System Integration Bus for the Modular Microscale Computing Class.
IEEE Micro, 2016

A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks.
J. Solid-State Circuits, 2016

An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations.
J. Solid-State Circuits, 2016

A 10 mm3 Inductive Coupling Radio for Syringe-Implantable Smart Sensor Nodes.
J. Solid-State Circuits, 2016

A Constant Energy-Per-Cycle Ring Oscillator Over a Wide Frequency Range for Wireless Sensor Nodes.
J. Solid-State Circuits, 2016

Battery Voltage Supervisors for Miniature IoT Systems.
J. Solid-State Circuits, 2016

A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory.
J. Solid-State Circuits, 2016

A Resonant Current-Mode Wireless Power Receiver and Battery Charger With -32 dBm Sensitivity for Implantable Systems.
J. Solid-State Circuits, 2016

A 110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3 ppm/°C Temperature Stability for System-on-Chip Designs.
J. Solid-State Circuits, 2016

A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering.
J. Solid-State Circuits, 2016

A Successive-Approximation Switched-Capacitor DC-DC Converter With Resolution of VIN/2N for a Wide Range of Input and Output Voltages.
J. Solid-State Circuits, 2016

Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes.
IEEE Journal on Selected Areas in Communications, 2016

A 66pW discontinuous switch-capacitor energy harvester for self-sustaining sensor applications.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 260µW infrared gesture recognition system-on-chip for smart devices.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 380pW dual mode optical wake-up receiver with ambient noise cancellation.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A Dual-Stage, Ultra-Low-Power Acoustic Event Detection System.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Millimeter-scale computing platform for next generation of Internet of Things.
Proceedings of the 2016 IEEE International Conference on RFID, 2016

8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

26.7 A 10mm3 syringe-implantable near-field radio system on glass substrate.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

21.4 A >78%-efficient light harvester over 100-to-100klux with reconfigurable PV-cell network and MPPT circuit.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedback.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

8.5 A 60%-efficiency 20nW-500µW tri-output fully integrated power management unit with environmental adaptation and load-proportional biasing for IoT systems.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

21.5 A current-mode wireless power receiver with optimal resonant cycle tracking for implantable systems.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Low complexity optical flow using neighbor-guided semi-global matching.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

A low power software-defined-radio baseband processor for the Internet of Things.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Supply boosting for high-performance processors in flip-chip packages.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
System-On-Mud: Ultra-Low Power Oceanic Sensing Platform Powered by Small-Scale Benthic Microbial Fuel Cells.
IEEE Trans. on Circuits and Systems, 2015

A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System.
J. Solid-State Circuits, 2015

A 5.8 nW CMOS Wake-Up Timer for Ultra-Low-Power Wireless Applications.
J. Solid-State Circuits, 2015

Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform.
J. Solid-State Circuits, 2015

SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS.
J. Solid-State Circuits, 2015

An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring.
J. Solid-State Circuits, 2015

A robust -40 to 120°C all-digital true random number generator in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

Circuits evening panel discussion 2: Wearable electronics: Still an oasis or just a mirage for the semiconductor industry?
Proceedings of the Symposium on VLSI Circuits, 2015

A 10.6mm3 fully-integrated, wireless sensor node with 8GHz UWB transmitter.
Proceedings of the Symposium on VLSI Circuits, 2015

A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications.
Proceedings of the Symposium on VLSI Circuits, 2015

A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory.
Proceedings of the Symposium on VLSI Circuits, 2015

A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell.
Proceedings of the Symposium on VLSI Circuits, 2015

Wide input range 1.7μW 1.2kS/s resistive sensor interface circuit with 1 cycle/sample logarithmic sub-ranging.
Proceedings of the Symposium on VLSI Circuits, 2015

A 99nW 70.4kHz resistive frequency locking on-chip oscillator with 27.4ppm/ºC temperature stability.
Proceedings of the Symposium on VLSI Circuits, 2015

A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple.
Proceedings of the Symposium on VLSI Circuits, 2015

A fixed-point neural network for keyword detection on resource constrained hardware.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

14.2 A physically unclonable function with BER-8 for robust chip authentication using oscillator collapse in 40nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

8.2 Batteryless Sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

27.6 A 0.7pF-to-10nF fully digital capacitance-to-digital converter using iterative delay-chain discharge.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Racetrack converter: A low power and compact data converter using racetrack spintronic devices.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

MBus: an ultra-low power interconnect bus for next generation nanopower systems.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

FOCUS: Key building blocks and integration strategy of a miniaturized wireless sensor node.
Proceedings of the ESSCIRC Conference 2015, 2015

All-digital SoC thermal sensor using on-chip high order temperature curvature correction.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

An ultra-low-power biomedical chip for injectable pressure monitor.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Design and Evaluation of Confidence-Driven Error-Resilient Systems.
IEEE Trans. VLSI Syst., 2014

Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM.
J. Solid-State Circuits, 2014

An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor Voltage Doubler.
J. Solid-State Circuits, 2014

A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes.
J. Solid-State Circuits, 2014

An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS.
J. Solid-State Circuits, 2014

A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS.
J. Solid-State Circuits, 2014

The Swarm at the Edge of the Cloud.
IEEE Design & Test, 2014

15.4b incremental sigma-delta capacitance-to-digital converter with zoom-in 9b asynchronous SAR.
Proceedings of the Symposium on VLSI Circuits, 2014

Low power battery supervisory circuit with adaptive battery health monitor.
Proceedings of the Symposium on VLSI Circuits, 2014

A millimeter-scale wireless imaging system with continuous motion detection and energy harvesting.
Proceedings of the Symposium on VLSI Circuits, 2014

A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recording.
Proceedings of the Symposium on VLSI Circuits, 2014

Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Energy-efficient dot product computation using a switched analog circuit architecture.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Chip-on-mud: Ultra-low power ARM-based oceanic sensing system powered by small-scale benthic microbial fuel cells.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Dual-slope capacitance to digital converter integrated in an implantable pressure sensing system.
Proceedings of the ESSCIRC 2014, 2014

A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs.
Proceedings of the ESSCIRC 2014, 2014

VIX: Virtual Input Crossbar for Efficient Switch Allocation.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Quality-of-Service for a High-Radix Switch.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Circuit techniques for miniaturized biomedical sensors.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

MBus: A 17.5 pJ/bit/chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 5.8nW, 45ppm/°C on-chip CMOS wake-up timer using a constant charge subtraction scheme.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 1.6nJ/bit, 19.9μA peak current fully integrated 2.5mm2 inductive transceiver for volume-constrained microsystems.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Mixed-signal stochastic computation demonstrated in an image sensor with integrated 2D edge detection and noise filtering.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs).
IEEE Trans. VLSI Syst., 2013

Achieving Ultralow Standby Power With an Efficient SCCMOS Bias Generator.
IEEE Trans. on Circuits and Systems, 2013

Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor.
IEEE Trans. on Circuits and Systems, 2013

A Low-Cost Audio Computer for Information Dissemination Among Illiterate People Groups.
IEEE Trans. on Circuits and Systems, 2013

A Statistical Framework for Post-Fabrication Oxide Breakdown Reliability Prediction and Management.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Limits of Parallelism and Boosting in Dim Silicon.
IEEE Micro, 2013

Centip3De: A 64-Core, 3D Stacked Near-Threshold System.
IEEE Micro, 2013

A Sub-nW Multi-stage Temperature Compensated Timer for Ultra-Low-Power Sensor Nodes.
J. Solid-State Circuits, 2013

A Modular 1 mm3 Die-Stacked Sensing Platform With Low Power I2C Inter-Die Communication and Multi-Modal Energy Harvesting.
J. Solid-State Circuits, 2013

A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells.
J. Solid-State Circuits, 2013

Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction.
J. Solid-State Circuits, 2013

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS.
J. Solid-State Circuits, 2013

Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes.
IPSJ Trans. System LSI Design Methodology, 2013

Centip3De: a many-core prototype exploring 3D integration and near-threshold computing.
Commun. ACM, 2013

M3: a mm-scale wireless energy harvesting sensor platform.
Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

Exploring DRAM organizations for energy-efficient and resilient exascale memories.
Proceedings of the International Conference for High Performance Computing, 2013

A 95fJ/b current-mode transceiver for 10mm on-chip interconnect.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolution.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A fully integrated switched-capacitor based PMU with adaptive energy harvesting technique for ultra-low power sensing applications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A low-power VGA full-frame feature extraction processor.
Proceedings of the IEEE International Conference on Acoustics, 2013

Scaling towards kilo-core processors with asymmetric high-radix topologies.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

65nW CMOS temperature sensor for ultra-low power microsystems.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

45pW ESD clamp circuit for ultra-low power applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation.
IEEE Trans. VLSI Syst., 2012

Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low ${V}_{\rm dd}$ Operation.
IEEE Trans. VLSI Syst., 2012

Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems.
IEEE Trans. on Circuits and Systems, 2012

A Reliable Routing Architecture and Algorithm for NoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V.
J. Solid-State Circuits, 2012

A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS.
J. Solid-State Circuits, 2012

Swizzle-Switch Networks for Many-Core Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A standard cell compatible bidirectional repeater with thyristor assist.
Proceedings of the Symposium on VLSI Circuits, 2012

A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM.
Proceedings of the Symposium on VLSI Circuits, 2012

A 635pW battery voltage supervisory circuit for miniature sensor nodes.
Proceedings of the Symposium on VLSI Circuits, 2012

A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold.
Proceedings of the Symposium on VLSI Circuits, 2012

Analysis and measurement of the stability of dual-resonator oscillators.
Proceedings of the 2012 IEEE Radio and Wireless Symposium, 2012

A 5.58nW 32.768kHz DLL-assisted XO for real-time clocks in wireless sensing applications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A modular 1mm3 die-stacked sensing platform with optical communication and multi-modal energy harvesting.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Bubble Razor: An architecture-independent approach to timing-error detection and correction.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Ultra-constrained sensor platform interfacing.
Proceedings of the 11th International Conference on Information Processing in Sensor Networks (co-located with CPS Week 2012), 2012

Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

SLC: Split-control Level Converter for dense and stable wide-range voltage conversion.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Process variation in near-threshold wide SIMD architectures.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Assessing the performance limits of parallelized near-threshold computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Circuit and system design guidelines for ultra-low power sensor nodes.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A 695 pW standby power optical wake-up receiver for wireless sensor nodes.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A low-cost audio computer for information dissemination among illiterate people groups.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Circuits for ultra-low power millimeter-scale sensor nodes.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect.
IEEE Trans. VLSI Syst., 2011

Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor.
IEEE Trans. on Circuits and Systems, 2011

Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS.
J. Solid-State Circuits, 2011

Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation".
J. Solid-State Circuits, 2011

A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation.
J. Solid-State Circuits, 2011

CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Robust Clock Network Design Methodology for Ultra-Low Voltage Operations.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A cubic-millimeter energy-autonomous wireless intraocular pressure monitor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A dense 45nm half-differential SRAM with lower minimum operating voltage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Energy-optimized high performance FFT processor.
Proceedings of the IEEE International Conference on Acoustics, 2011

Low power interconnects for SIMD computers.
Proceedings of the Design, Automation and Test in Europe, 2011

A confidence-driven model for error-resilient computing.
Proceedings of the Design, Automation and Test in Europe, 2011

Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design.
Proceedings of the 48th Design Automation Conference, 2011

2010
Yield-Driven Near-Threshold SRAM Design.
IEEE Trans. VLSI Syst., 2010

Mechanical Stress Aware Optimization for Leakage Power Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Victim Alignment in Crosstalk-Aware Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits.
Proceedings of the IEEE, 2010

Circuit Design Advances for Wireless Sensing Applications.
Proceedings of the IEEE, 2010

Securing Encryption Systems With a Switched Capacitor Current Equalizer.
J. Solid-State Circuits, 2010

A 0.5 V Sub-Microwatt CMOS Image Sensor With Pulse-Width Modulation Read-Out.
J. Solid-State Circuits, 2010

Early detection of oxide breakdown through in situ degradation sensing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Clock network design for ultra-low power applications.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Circuit design advances to enable ubiquitous sensing environments.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Active learning framework for post-silicon variation extraction and test cost reduction.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A lower bound computation method for evaluation of statistical design techniques.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Analysis and optimization of SRAM robustness for double patterning lithography.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A case for custom silicon in enabling low-cost information technology for developing regions.
Proceedings of the First ACM Annual Symposium on Computing for Development, 2010

Process variation and temperature-aware reliability management.
Proceedings of the Design, Automation and Test in Europe, 2010

A black box method for stability analysis of arbitrary SRAM cell structures.
Proceedings of the Design, Automation and Test in Europe, 2010

Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization.
Proceedings of the 47th Design Automation Conference, 2010

Closed-form modeling of layout-dependent mechanical stress.
Proceedings of the 47th Design Automation Conference, 2010

Dynamic NBTI management using a 45nm multi-degradation sensor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Ultra-low power circuit techniques for a new class of sub-mm3 sensor nodes.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Design time body bias selection for parametric yield improvement.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Analyzing electrical effects of RTA-driven local anneal temperature variation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Energy-Efficient Subthreshold Processor Design.
IEEE Trans. VLSI Syst., 2009

Circuit optimization techniques to mitigate the effects of soft errors in combinational logic.
ACM Trans. Design Autom. Electr. Syst., 2009

Alignment-Independent Chip-to-Chip Communication for Sensor Applications Using Passive Capacitive Signaling.
J. Solid-State Circuits, 2009

A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode.
J. Solid-State Circuits, 2009

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance.
J. Solid-State Circuits, 2009

Sensor-Driven Reliability and Wearout Management.
IEEE Design & Test of Computers, 2009

Reconfigurable Multicore Server Processors for Low Power Operation.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Secure AES engine with a local switched-capacitor current equalizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 150pW program-and-hold timer for ultra-low-power sensor platforms.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Low power circuit design based on heterojunction tunneling transistors (HETTs).
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Adaptive Design for Nanometer Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Interconnect performance corners considering crosstalk noise.
Proceedings of the 27th International Conference on Computer Design, 2009

Post-fabrication measurement-driven oxide breakdown reliability prediction and management.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A highly resilient routing algorithm for fault-tolerant NoCs.
Proceedings of the Design, Automation and Test in Europe, 2009

Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence.
Proceedings of the 46th Design Automation Conference, 2009

Worst-case aggressor-victim alignment with current-source driver models.
Proceedings of the 46th Design Automation Conference, 2009

Vicis: a reliable network for unreliable silicon.
Proceedings of the 46th Design Automation Conference, 2009

Addressing design margins through error-tolerant circuits.
Proceedings of the 46th Design Automation Conference, 2009

A 0.5V 2.2pW 2-transistor voltage reference.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Near-field communication using phase-locking and pulse signaling for millimeter-scale systems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect.
IEEE Trans. VLSI Syst., 2008

Multi-Mechanism Reliability Modeling and Management in Dynamic Systems.
IEEE Trans. VLSI Syst., 2008

A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Statistical Timing Analysis: From Basic Principles to State of the Art.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM.
J. Solid-State Circuits, 2008

True Random Number Generator With a Metastability-Based Quality Control.
J. Solid-State Circuits, 2008

Exploring Variability and Performance in a Sub-200-mV Processor.
J. Solid-State Circuits, 2008

Reconfigurable energy efficient near threshold cache architectures.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

A Charge-Injection-Based Active-Decoupling Technique for Inductive-Supply-Noise Suppression.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Fast and Accurate Waveform Analysis with Current Source Models.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Stress aware layout optimization.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Variation-aware gate sizing and clustering for post-silicon optimized circuits.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Optimal technology selection for minimizing energy and variability in low voltage applications.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Low-voltage circuit design for widespread sensing applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

On the decreasing significance of large standard cells in technology mapping.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

STEEL: a technique for stress-enhanced standard cell library design.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A statistical approach for full-chip gate-oxide reliability analysis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Transistor-Specific Delay Modeling for SSTA.
Proceedings of the Design, Automation and Test in Europe, 2008

Efficient Monte Carlo based incremental statistical timing analysis.
Proceedings of the 45th Design Automation Conference, 2008

Leakage power reduction using stress-enhanced layouts.
Proceedings of the 45th Design Automation Conference, 2008

Modeling crosstalk in statistical static timing analysis.
Proceedings of the 45th Design Automation Conference, 2008

Timing yield enhancement through soft edge flip-flop based design.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Robust ultra-low voltage ROM design.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

An ultra low power 1V, 220nW temperature sensor for passive wireless applications.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Power Grid Physics and Implications for CAD.
IEEE Design & Test of Computers, 2007

Statistical Timing Based Optimization using Gate Sizing
CoRR, 2007

DVS for On-Chip Bus Designs Based on Timing Error Correction
CoRR, 2007

Crosstalk Waveform Modeling Using Wave Fitting.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Sub-200mV 6T SRAM in 0.13μm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

True Random Number Generator with a Metastability-Based Quality Control.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Digital Circuit Innovations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Self-Time Regenerators for High-Speed and Low-Power Interconnect.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Investigating Crosstalk in Sub-Threshold Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Energy efficient near-threshold chip multi-processing.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A robust edge encoding technique for energy-efficient multi-cycle interconnect.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Soft-edge flip-flops for improved timing yield: design and optimization.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Victim alignment in crosstalk aware timing analysis.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Yield-driven near-threshold SRAM design.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design.
Proceedings of the 44th Design Automation Conference, 2007

Nanometer Device Scaling in Subthreshold Circuits.
Proceedings of the 44th Design Automation Conference, 2007

Top-k Aggressors Sets in Delay Noise Analysis.
Proceedings of the 44th Design Automation Conference, 2007

A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

An Energy Efficient Parallel Architecture Using Near Threshold Operation.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Runtime Leakage Minimization Through Probability-Aware Optimization.
IEEE Trans. VLSI Syst., 2006

Analytical yield prediction considering leakage/performance correlation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Modeling and analysis of crosstalk noise in coupled RLC interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Statistical interconnect metrics for physical-design optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Ultralow-voltage, minimum-energy CMOS.
IBM Journal of Research and Development, 2006

ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon.
IEEE Design & Test of Computers, 2006

Receiver Modeling for Static Functional Crosstalk Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Logic SER Reduction through Flipflop Redesign.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Energy optimality and variability in subthreshold design.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Energy efficient design for subthreshold supply voltage operation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Soft error reduction in combinational logic using gate resizing and flipflop selection.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A statistical framework for post-silicon tuning through body bias clustering.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Analysis and modeling of CD variation for statistical static timing.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A new statistical max operation for propagating skewness in statistical timing analysis.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

An efficient static algorithm for computing the soft error rates of combinational circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Reliability modeling and management in dynamic microprocessor-based systems.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Statistical Analysis and Optimization for VLSI: Timing and Power
Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-26528-5, 2005

The limit of dynamic voltage scaling and insomniac dynamic voltage scaling.
IEEE Trans. VLSI Syst., 2005

Bus encoding for total power reduction using a leakage-aware buffer configuration.
IEEE Trans. VLSI Syst., 2005

Quantitative analysis and optimization techniques for on-chip cache leakage power.
IEEE Trans. VLSI Syst., 2005

Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Probability distribution of signal arrival times using Bayesian networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Modeling and Analysis of Parametric Yield under Power and Performance Constraints.
IEEE Design & Test of Computers, 2005

Error Analysis for the Support of Robust Voltage Scaling.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Leakage Current Modeling in PD SOI Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

An efficient surface-based low-power buffer insertion algorithm.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Analysis and mitigation of variability in subthreshold design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Timing error correction techniques for voltage-scalable on-chip memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Energy Optimization of Subthreshold-Voltage Sensor Network Processors.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Discrete Vt assignment and gate sizing using a self-snapping continuous formulation.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Static timing analysis considering power supply variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Accurate delay computation for noisy waveform shapes.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Slack borrowing in flip-flop based sequential circuits.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

DVS for On-Chip Bus Designs Based on Timing Error Correction.
Proceedings of the 2005 Design, 2005

Statistical Timing Based Optimization using Gate Sizing.
Proceedings of the 2005 Design, 2005

Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.
Proceedings of the 42nd Design Automation Conference, 2005

CAD tools for variation tolerance.
Proceedings of the 42nd Design Automation Conference, 2005

Circuit optimization using statistical static timing analysis.
Proceedings of the 42nd Design Automation Conference, 2005

A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution.
Proceedings of the 2005 International Conference on Compilers, 2005

Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Leakage power: trends, analysis and avoidance.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Opportunities and challenges for better than worst-case design.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Achieving continuous VT performance in a dual VT process.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Statistical modeling of cross-coupling effects in VLSI interconnects.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Statistical analysis of subthreshold leakage current for VLSI circuits.
IEEE Trans. VLSI Syst., 2004

Gate oxide leakage current analysis and reduction for VLSI circuits.
IEEE Trans. VLSI Syst., 2004

Circuit and microarchitectural techniques for reducing cache leakage power.
IEEE Trans. VLSI Syst., 2004

Performance optimization of critical nets through active shielding.
IEEE Trans. on Circuits and Systems, 2004

Postroute gate sizing for crosstalk noise reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Statistical clock skew analysis considering intradie-process variations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

A simple metric for slew rate of RC circuits based on two circuit moments.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

A library compatible driver output model for on-chip RLC transmission lines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation.
IEEE Micro, 2004

Mobile Supercomputers.
IEEE Computer, 2004

Making Typical Silicon Matter with Razor.
IEEE Computer, 2004

Extended dynamic voltage scaling for low power design.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Reducing pipeline energy demands with local DVS and dynamic retiming.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design.
Proceedings of the 2004 Design, 2004

Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization.
Proceedings of the 2004 Design, 2004

Theoretical and practical limits of dynamic voltage scaling.
Proceedings of the 41th Design Automation Conference, 2004

Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.
Proceedings of the 41th Design Automation Conference, 2004

Statistical optimization of leakage power considering process variations using dual-Vth and sizing.
Proceedings of the 41th Design Automation Conference, 2004

Parametric yield estimation considering leakage variability.
Proceedings of the 41th Design Automation Conference, 2004

A stochastic approach To power grid analysis.
Proceedings of the 41th Design Automation Conference, 2004

Static timing analysis using backward signal propagation.
Proceedings of the 41th Design Automation Conference, 2004

Circuit-aware architectural simulation.
Proceedings of the 41th Design Automation Conference, 2004

Leakage-and crosstalk-aware bus encoding for total power reduction.
Proceedings of the 41th Design Automation Conference, 2004

Variational delay metrics for interconnect timing analysis.
Proceedings of the 41th Design Automation Conference, 2004

Statistical gate delay model considering multiple input switching.
Proceedings of the 41th Design Automation Conference, 2004

A simplified transmission-line based crosstalk noise model for on-chip RLC wiring.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Static Leakage Reduction through Simulteneous VTT/TOX and State Assignment.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Driver modeling and alignment for worst-case delay noise.
IEEE Trans. VLSI Syst., 2003

Probabilistic analysis of interconnect coupling noise.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Fast on-chip inductance simulation using a precorrected-FFT method.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Accurate crosstalk noise modeling for early signal integrity analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Static electromigration analysis for on-chip signal interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Early probabilistic noise estimation for capacitively coupled interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Statistical timing analysis using bounds and selective enumeration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Impact of Low-Impedance Substrate on Power Supply Integrity.
IEEE Design & Test of Computers, 2003

Leakage Current: Moore's Law Meets Static Power.
IEEE Computer, 2003

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Static Electromigration Analysis for Signal Interconnects.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Statistical estimation of leakage current considering inter- and intra-die process variation.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Table look-up based compact modeling for on-chip interconnect timing and noise analysis.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Optimal Inductance for On-chip RLC Interconnections.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Vectorless Analysis of Supply Noise Induced Delay Variation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

SOI Transistor Model for Fast Transient Simulation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

AU: Timing Analysis Under Uncertainty.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical Clock Skew Analysis Considering Intra-Die Process Variations.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical Timing Analysis Using Bounds.
Proceedings of the 2003 Design, 2003

Non-iterative switching window computation for delay-noise.
Proceedings of the 40th Design Automation Conference, 2003

Reshaping EDA for power.
Proceedings of the 40th Design Automation Conference, 2003

Analysis and minimization techniques for total leakage considering gate oxide leakage.
Proceedings of the 40th Design Automation Conference, 2003

Static leakage reduction through simultaneous threshold voltage and state assignment.
Proceedings of the 40th Design Automation Conference, 2003

Post-route gate sizing for crosstalk noise reduction.
Proceedings of the 40th Design Automation Conference, 2003

Simple metrics for slew rate of RC circuits based on two circuit moments.
Proceedings of the 40th Design Automation Conference, 2003

An effective capacitance based driver output model for on-chip RLC interconnects.
Proceedings of the 40th Design Automation Conference, 2003

Computation and Refinement of Statistical Bounds on Circuit Delay.
Proceedings of the 40th Design Automation Conference, 2003

Statistical delay computation considering spatial correlations.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits.
IEEE Trans. VLSI Syst., 2002

Inductance model and analysis methodology for high-speed on-chip interconnect.
IEEE Trans. VLSI Syst., 2002

False-noise analysis using logic implications.
ACM Trans. Design Autom. Electr. Syst., 2002

Hierarchical analysis of power distribution networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Slope propagation in static timing analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Leakage Current Reduction in VLSI Systems.
Journal of Circuits, Systems, and Computers, 2002

Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference.
IEEE Design & Test of Computers, 2002

Efficient switching window computation for cross-talk noise.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Active shielding of RLC global interconnects.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

A library compatible driving point model for on-chip RLC interconnects.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Statistical timing analysis using bounds and selective enumeration.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Early probabilistic noise estimation for capacitively coupled interconnects.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

Robust SAT-Based Search Algorithm for Leakage Power Reduction.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Noise Injection and Propagation in High Performance Designs.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

False-Noise Analysis Using Resolution Method.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Pre-route Noise Estimation in Deep Submicron Integrated Circuits.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Modeling and analysis of leakage power considering within-die process variations.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Crosstalk noise estimation using effective coupling capacitance.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Drowsy Caches: Simple Techniques for Reducing Leakage Power.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Noise propagation and failure criteria for VLSI designs.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A precorrected-FFT method for simulating on-chip inductance.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Efficient crosstalk noise modeling using aggressor and tree reductions.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Estimation of signal arrival times in the presence of delay noise.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Active shields: a new approach to shielding global wires.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .
Proceedings of the 2002 Design, 2002

Estimation of the likelihood of capacitive coupling noise.
Proceedings of the 39th Design Automation Conference, 2002

2001
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

On the interaction of power distribution network with substrate.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

False-Noise Analysis using Logic Implications.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Driver Modeling and Alignment for Worst-Case Delay Noise.
Proceedings of the 38th Design Automation Conference, 2001

Inductance 101: Analysis and Design Issues.
Proceedings of the 38th Design Automation Conference, 2001

2000
Design and Analysis of Power Distribution Networks with Accurate RLC Models.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Model and analysis for combined package and on-chip power grid simulation.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Slope Propagation in Static Timing Analysis.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

On-chip inductance modeling.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Hierarchical analysis of power distribution networks.
Proceedings of the 37th Conference on Design Automation, 2000

ClariNet: a noise analysis tool for deep submicron design.
Proceedings of the 37th Conference on Design Automation, 2000

On-chip inductance modeling and analysis.
Proceedings of the 37th Conference on Design Automation, 2000

Current signature compression for IR-drop analysis.
Proceedings of the 37th Conference on Design Automation, 2000

Removing user specified false paths from timing graphs.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Timing and Signal Integrity Analysis.
Proceedings of the VLSI Handbook., 1999

A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Emerging power management tools for processor design.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization.
Proceedings of the 35th Conference on Design Automation, 1998

Design and Analysis of Power Distribution Networks in PowerPC Microprocessors.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Library-less synthesis for static CMOS combinational logic circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fast power loss calculation for digital static CMOS circuits.
Proceedings of the European Design and Test Conference, 1997

1995
Transistor reordering for low power CMOS gates using an SP-BDD representation.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1994
A cache-based method for accelerating switch-level simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

1991
Functional abstraction of logic gates for switch-level simulation.
Proceedings of the conference on European design automation, 1991

1990
Hierarchical multi-level fault simulation of large systems.
J. Electronic Testing, 1990

Fault grading of large digital systems.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Automatic classification of node types in switch-level descriptions.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Derivation of signal flow for switch-level simulation.
Proceedings of the European Design Automation Conference, 1990

1989
Automatic Generation of Behavioral Models from Switch-Level Descriptions.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988


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