Shidhartha Das

According to our database1, Shidhartha Das authored at least 55 papers between 2003 and 2019.

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Bibliography

2019
Design and Optimization of Inductive-Coupling Links for 3-D-ICs.
IEEE Trans. VLSI Syst., 2019

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.
IEEE Trans. VLSI Syst., 2019

Training DNN IoT Applications for Deployment On Analog NVM Crossbars.
CoRR, 2019

Neural Network Design for Energy-Autonomous AI Applications using Temporal Encoding.
CoRR, 2019

GeST: An Automatic Framework For Generating CPU Stress-Tests.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Run-time Detection and Mitigation of Power-Noise Viruses.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

Applications of Computation-In-Memory Architectures based on Memristive Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Time-Domain Current-Mode MAC Engine for Analogue Neural Networks in Flexible Electronics.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
Real-Power Computing.
IEEE Trans. Computers, 2018

Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC).
J. Solid-State Circuits, 2018

Significance-Driven Logic Compression for Energy-Efficient Multiplier Design.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Sensing CPU Voltage Noise Through Electromagnetic Emanations.
Computer Architecture Letters, 2018

Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018


Low-power 3D integration using inductive coupling links for neurotechnology applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A high-speed design methodology for inductive coupling links in 3D-ICs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor.
J. Solid-State Circuits, 2017

Error-Resilient Server Ecosystems for Edge and Cloud Datacenters.
IEEE Computer, 2017

Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Harnessing voltage margins for energy efficiency in multicore CPUs.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Frequency and time domain analysis of power delivery network for monolithic 3D ICs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Hardware and software innovations in energy-efficient system-reliability monitoring.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches.
IET Computers & Digital Techniques, 2016

A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016

2015
A 0.6V all-digital body-coupled wakeup transceiver for IoT applications.
Proceedings of the Symposium on VLSI Circuits, 2015

14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Analysis of adaptive clocking technique for resonant supply voltage noise mitigation.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation.
IEEE Trans. on Circuits and Systems, 2014

A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS.
J. Solid-State Circuits, 2014

2013
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms.
IEEE Trans. VLSI Syst., 2013

A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Selective time borrowing for DSP pipelines with hybrid voltage control loop.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation".
J. Solid-State Circuits, 2011

A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation.
J. Solid-State Circuits, 2011

Error-resilient low-power DSP via path-delay shaping.
Proceedings of the 48th Design Automation Conference, 2011

2010
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A robust FIR filter with in situ error detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance.
J. Solid-State Circuits, 2009

Adaptive Design for Nanometer Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Addressing design margins through error-tolerant circuits.
Proceedings of the 46th Design Automation Conference, 2009

2008
Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

DVFS in loop accelerators using BLADES.
Proceedings of the 45th Design Automation Conference, 2008

2004
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation.
IEEE Micro, 2004

Reducing pipeline energy demands with local DVS and dynamic retiming.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Circuit-aware architectural simulation.
Proceedings of the 41th Design Automation Conference, 2004

2003
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Optimal Inductance for On-chip RLC Interconnections.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003


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